forked from luck/tmp_suning_uos_patched
ARM: OMAP2+: CM: AM43x clockdomain data
Add the data file to describe clock domains in AM43x SoC. OMAP4 clockdomain operations is being reused here. Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Afzal Mohammed <afzal@ti.com> Acked-by: Rajendra Nayak <rnayak@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
Ambresh K
Paul Walmsley
parent
eadc62fc43
commit
c9218fe63f
@ -218,6 +218,7 @@ extern void __init am33xx_clockdomains_init(void);
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extern void __init omap44xx_clockdomains_init(void);
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extern void __init omap54xx_clockdomains_init(void);
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extern void __init dra7xx_clockdomains_init(void);
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void am43xx_clockdomains_init(void);
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extern void clkdm_add_autodeps(struct clockdomain *clkdm);
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extern void clkdm_del_autodeps(struct clockdomain *clkdm);
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@ -226,6 +227,7 @@ extern struct clkdm_ops omap2_clkdm_operations;
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extern struct clkdm_ops omap3_clkdm_operations;
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extern struct clkdm_ops omap4_clkdm_operations;
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extern struct clkdm_ops am33xx_clkdm_operations;
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extern struct clkdm_ops am43xx_clkdm_operations;
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extern struct clkdm_dep gfx_24xx_wkdeps[];
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extern struct clkdm_dep dsp_24xx_wkdeps[];
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196
arch/arm/mach-omap2/clockdomains43xx_data.c
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196
arch/arm/mach-omap2/clockdomains43xx_data.c
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@ -0,0 +1,196 @@
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/*
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* AM43xx Clock domains framework
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include "clockdomain.h"
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#include "prcm44xx.h"
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#include "prcm43xx.h"
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static struct clockdomain l4_cefuse_43xx_clkdm = {
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.name = "l4_cefuse_clkdm",
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.pwrdm = { .name = "cefuse_pwrdm" },
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.prcm_partition = AM43XX_CM_PARTITION,
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.cm_inst = AM43XX_CM_CEFUSE_INST,
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.clkdm_offs = AM43XX_CM_CEFUSE_CEFUSE_CDOFFS,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain mpu_43xx_clkdm = {
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.name = "mpu_clkdm",
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.pwrdm = { .name = "mpu_pwrdm" },
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.prcm_partition = AM43XX_CM_PARTITION,
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.cm_inst = AM43XX_CM_MPU_INST,
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.clkdm_offs = AM43XX_CM_MPU_MPU_CDOFFS,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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};
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static struct clockdomain l4ls_43xx_clkdm = {
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.name = "l4ls_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.prcm_partition = AM43XX_CM_PARTITION,
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.cm_inst = AM43XX_CM_PER_INST,
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.clkdm_offs = AM43XX_CM_PER_L4LS_CDOFFS,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain tamper_43xx_clkdm = {
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.name = "tamper_clkdm",
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.pwrdm = { .name = "tamper_pwrdm" },
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.prcm_partition = AM43XX_CM_PARTITION,
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.cm_inst = AM43XX_CM_TAMPER_INST,
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.clkdm_offs = AM43XX_CM_TAMPER_TAMPER_CDOFFS,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain l4_rtc_43xx_clkdm = {
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.name = "l4_rtc_clkdm",
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.pwrdm = { .name = "rtc_pwrdm" },
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.prcm_partition = AM43XX_CM_PARTITION,
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.cm_inst = AM43XX_CM_RTC_INST,
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.clkdm_offs = AM43XX_CM_RTC_RTC_CDOFFS,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain pruss_ocp_43xx_clkdm = {
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.name = "pruss_ocp_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.prcm_partition = AM43XX_CM_PARTITION,
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.cm_inst = AM43XX_CM_PER_INST,
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.clkdm_offs = AM43XX_CM_PER_ICSS_CDOFFS,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain ocpwp_l3_43xx_clkdm = {
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.name = "ocpwp_l3_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.prcm_partition = AM43XX_CM_PARTITION,
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.cm_inst = AM43XX_CM_PER_INST,
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.clkdm_offs = AM43XX_CM_PER_OCPWP_L3_CDOFFS,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain l3s_tsc_43xx_clkdm = {
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.name = "l3s_tsc_clkdm",
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.pwrdm = { .name = "wkup_pwrdm" },
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.prcm_partition = AM43XX_CM_PARTITION,
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.cm_inst = AM43XX_CM_WKUP_INST,
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.clkdm_offs = AM43XX_CM_WKUP_L3S_TSC_CDOFFS,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain dss_43xx_clkdm = {
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.name = "dss_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.prcm_partition = AM43XX_CM_PARTITION,
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.cm_inst = AM43XX_CM_PER_INST,
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.clkdm_offs = AM43XX_CM_PER_DSS_CDOFFS,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain l3_aon_43xx_clkdm = {
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.name = "l3_aon_clkdm",
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.pwrdm = { .name = "wkup_pwrdm" },
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.prcm_partition = AM43XX_CM_PARTITION,
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.cm_inst = AM43XX_CM_WKUP_INST,
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.clkdm_offs = AM43XX_CM_WKUP_L3_AON_CDOFFS,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain emif_43xx_clkdm = {
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.name = "emif_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.prcm_partition = AM43XX_CM_PARTITION,
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.cm_inst = AM43XX_CM_PER_INST,
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.clkdm_offs = AM43XX_CM_PER_EMIF_CDOFFS,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain l4_wkup_aon_43xx_clkdm = {
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.name = "l4_wkup_aon_clkdm",
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.pwrdm = { .name = "wkup_pwrdm" },
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.prcm_partition = AM43XX_CM_PARTITION,
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.cm_inst = AM43XX_CM_WKUP_INST,
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.clkdm_offs = AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS,
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};
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static struct clockdomain l3_43xx_clkdm = {
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.name = "l3_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.prcm_partition = AM43XX_CM_PARTITION,
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.cm_inst = AM43XX_CM_PER_INST,
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.clkdm_offs = AM43XX_CM_PER_L3_CDOFFS,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain l4_wkup_43xx_clkdm = {
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.name = "l4_wkup_clkdm",
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.pwrdm = { .name = "wkup_pwrdm" },
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.prcm_partition = AM43XX_CM_PARTITION,
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.cm_inst = AM43XX_CM_WKUP_INST,
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.clkdm_offs = AM43XX_CM_WKUP_WKUP_CDOFFS,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain cpsw_125mhz_43xx_clkdm = {
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.name = "cpsw_125mhz_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.prcm_partition = AM43XX_CM_PARTITION,
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.cm_inst = AM43XX_CM_PER_INST,
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.clkdm_offs = AM43XX_CM_PER_CPSW_CDOFFS,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain gfx_l3_43xx_clkdm = {
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.name = "gfx_l3_clkdm",
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.pwrdm = { .name = "gfx_pwrdm" },
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.prcm_partition = AM43XX_CM_PARTITION,
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.cm_inst = AM43XX_CM_GFX_INST,
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.clkdm_offs = AM43XX_CM_GFX_GFX_L3_CDOFFS,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain l3s_43xx_clkdm = {
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.name = "l3s_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.prcm_partition = AM43XX_CM_PARTITION,
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.cm_inst = AM43XX_CM_PER_INST,
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.clkdm_offs = AM43XX_CM_PER_L3S_CDOFFS,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain *clockdomains_am43xx[] __initdata = {
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&l4_cefuse_43xx_clkdm,
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&mpu_43xx_clkdm,
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&l4ls_43xx_clkdm,
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&tamper_43xx_clkdm,
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&l4_rtc_43xx_clkdm,
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&pruss_ocp_43xx_clkdm,
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&ocpwp_l3_43xx_clkdm,
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&l3s_tsc_43xx_clkdm,
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&dss_43xx_clkdm,
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&l3_aon_43xx_clkdm,
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&emif_43xx_clkdm,
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&l4_wkup_aon_43xx_clkdm,
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&l3_43xx_clkdm,
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&l4_wkup_43xx_clkdm,
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&cpsw_125mhz_43xx_clkdm,
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&gfx_l3_43xx_clkdm,
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&l3s_43xx_clkdm,
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NULL
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};
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void __init am43xx_clockdomains_init(void)
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{
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clkdm_register_platform_funcs(&am43xx_clkdm_operations);
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clkdm_register_clkdms(clockdomains_am43xx);
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clkdm_complete_init();
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}
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@ -483,3 +483,12 @@ struct clkdm_ops omap4_clkdm_operations = {
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.clkdm_clk_enable = omap4_clkdm_clk_enable,
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.clkdm_clk_disable = omap4_clkdm_clk_disable,
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};
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struct clkdm_ops am43xx_clkdm_operations = {
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.clkdm_sleep = omap4_clkdm_sleep,
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.clkdm_wakeup = omap4_clkdm_wakeup,
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.clkdm_allow_idle = omap4_clkdm_allow_idle,
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.clkdm_deny_idle = omap4_clkdm_deny_idle,
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.clkdm_clk_enable = omap4_clkdm_clk_enable,
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.clkdm_clk_disable = omap4_clkdm_clk_disable,
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};
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