forked from luck/tmp_suning_uos_patched
[ARM] 4582/2: Add support for the common VFP subarchitecture
This patch allows the VFP support code to run correctly on CPUs compatible with the common VFP subarchitecture specification (Appendix B in the ARM ARM v7-A and v7-R edition). It implements support for VFP subarchitecture 2 while being backwards compatible with subarchitecture 1. On VFP subarchitecture 1, the arithmetic exceptions are asynchronous (or imprecise as described in the old ARM ARM) unless the FPSCR.IXE bit is 1. The exceptional instructions can be read from FPINST and FPINST2 registers. With VFP subarchitecture 2, the arithmetic exceptions can also be synchronous and marked by the FPEXC.DEX bit (the FPEXC.EX bit is cleared). CPUs implementing the synchronous arithmetic exceptions don't have the FPINST and FPINST2 registers and accessing them would trigger and undefined exception. Note that FPEXC.EX bit has an additional meaning on subarchitecture 1 - if it isn't set, there is no additional information in FPINST and FPINST2 that needs to be saved at context switch or when lazy-loading the VFP state of a different thread. The patch also removes the clearing of the cumulative exception flags in FPSCR when additional exceptions were raised. It is up to the user application to clear these bits. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Catalin Marinas
Russell King
parent
9b73e76f3c
commit
c98929c07a
@ -100,10 +100,10 @@ vfp_support_entry:
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cmp r4, #0
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beq no_old_VFP_process
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VFPFMRX r5, FPSCR @ current status
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VFPFMRX r6, FPINST @ FPINST (always there, rev0 onwards)
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tst r1, #FPEXC_FPV2 @ is there an FPINST2 to read?
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VFPFMRX r8, FPINST2, NE @ FPINST2 if needed - avoids reading
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@ nonexistant reg on rev0
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tst r1, #FPEXC_EX @ is there additional state to save?
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VFPFMRX r6, FPINST, NE @ FPINST (only if FPEXC.EX is set)
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tstne r1, #FPEXC_FP2V @ is there an FPINST2 to read?
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VFPFMRX r8, FPINST2, NE @ FPINST2 if needed (and present)
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VFPFSTMIA r4 @ save the working registers
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stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
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@ and point r4 at the word at the
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@ -117,10 +117,10 @@ no_old_VFP_process:
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VFPFLDMIA r10 @ reload the working registers while
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@ FPEXC is in a safe state
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ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
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tst r1, #FPEXC_FPV2 @ is there an FPINST2 to write?
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VFPFMXR FPINST2, r8, NE @ FPINST2 if needed - avoids writing
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@ nonexistant reg on rev0
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VFPFMXR FPINST, r6
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tst r1, #FPEXC_EX @ is there additional state to restore?
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VFPFMXR FPINST, r6, NE @ restore FPINST (only if FPEXC.EX is set)
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tstne r1, #FPEXC_FP2V @ is there an FPINST2 to write?
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VFPFMXR FPINST2, r8, NE @ FPINST2 if needed (and present)
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VFPFMXR FPSCR, r5 @ restore status
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check_for_exception:
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@ -136,10 +136,14 @@ check_for_exception:
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look_for_VFP_exceptions:
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tst r1, #FPEXC_EX
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@ Check for synchronous or asynchronous exception
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tst r1, #FPEXC_EX | FPEXC_DEX
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bne process_exception
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@ On some implementations of the VFP subarch 1, setting FPSCR.IXE
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@ causes all the CDP instructions to be bounced synchronously without
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@ setting the FPEXC.EX bit
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VFPFMRX r5, FPSCR
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tst r5, #FPSCR_IXE @ IXE doesn't set FPEXC_EX !
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tst r5, #FPSCR_IXE
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bne process_exception
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@ Fall into hand on to next handler - appropriate coproc instr
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@ -150,10 +154,6 @@ look_for_VFP_exceptions:
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process_exception:
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DBGSTR "bounce"
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sub r2, r2, #4
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str r2, [sp, #S_PC] @ retry the instruction on exit from
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@ the imprecise exception handling in
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@ the support code
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mov r2, sp @ nothing stacked - regdump is at TOS
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mov lr, r9 @ setup for a return to the user code.
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@ -161,7 +161,7 @@ process_exception:
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@ r0 holds the trigger instruction
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@ r1 holds the FPEXC value
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@ r2 pointer to register dump
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b VFP9_bounce @ we have handled this - the support
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b VFP_bounce @ we have handled this - the support
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@ code will raise an exception if
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@ required. If not, the user code will
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@ retry the faulted instruction
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@ -175,10 +175,10 @@ vfp_save_state:
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@ r1 - FPEXC
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DBGSTR1 "save VFP state %p", r0
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VFPFMRX r2, FPSCR @ current status
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VFPFMRX r3, FPINST @ FPINST (always there, rev0 onwards)
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tst r1, #FPEXC_FPV2 @ is there an FPINST2 to read?
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VFPFMRX r12, FPINST2, NE @ FPINST2 if needed - avoids reading
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@ nonexistant reg on rev0
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tst r1, #FPEXC_EX @ is there additional state to save?
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VFPFMRX r3, FPINST, NE @ FPINST (only if FPEXC.EX is set)
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tstne r1, #FPEXC_FP2V @ is there an FPINST2 to read?
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VFPFMRX r12, FPINST2, NE @ FPINST2 if needed (and present)
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VFPFSTMIA r0 @ save the working registers
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stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2
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mov pc, lr
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@ -125,13 +125,13 @@ void vfp_raise_sigfpe(unsigned int sicode, struct pt_regs *regs)
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send_sig_info(SIGFPE, &info, current);
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}
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static void vfp_panic(char *reason)
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static void vfp_panic(char *reason, u32 inst)
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{
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int i;
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printk(KERN_ERR "VFP: Error: %s\n", reason);
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printk(KERN_ERR "VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n",
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fmrx(FPEXC), fmrx(FPSCR), fmrx(FPINST));
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fmrx(FPEXC), fmrx(FPSCR), inst);
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for (i = 0; i < 32; i += 2)
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printk(KERN_ERR "VFP: s%2u: 0x%08x s%2u: 0x%08x\n",
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i, vfp_get_float(i), i+1, vfp_get_float(i+1));
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@ -147,19 +147,16 @@ static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_
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pr_debug("VFP: raising exceptions %08x\n", exceptions);
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if (exceptions == VFP_EXCEPTION_ERROR) {
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vfp_panic("unhandled bounce");
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vfp_panic("unhandled bounce", inst);
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vfp_raise_sigfpe(0, regs);
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return;
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}
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/*
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* If any of the status flags are set, update the FPSCR.
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* Update the FPSCR with the additional exception flags.
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* Comparison instructions always return at least one of
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* these flags set.
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*/
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if (exceptions & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V))
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fpscr &= ~(FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V);
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fpscr |= exceptions;
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fmxr(FPSCR, fpscr);
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@ -220,35 +217,64 @@ static u32 vfp_emulate_instruction(u32 inst, u32 fpscr, struct pt_regs *regs)
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/*
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* Package up a bounce condition.
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*/
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void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
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void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
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{
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u32 fpscr, orig_fpscr, exceptions, inst;
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u32 fpscr, orig_fpscr, fpsid, exceptions;
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pr_debug("VFP: bounce: trigger %08x fpexc %08x\n", trigger, fpexc);
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/*
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* Enable access to the VFP so we can handle the bounce.
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* At this point, FPEXC can have the following configuration:
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*
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* EX DEX IXE
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* 0 1 x - synchronous exception
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* 1 x 0 - asynchronous exception
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* 1 x 1 - sychronous on VFP subarch 1 and asynchronous on later
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* 0 0 1 - synchronous on VFP9 (non-standard subarch 1
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* implementation), undefined otherwise
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*
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* Clear various bits and enable access to the VFP so we can
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* handle the bounce.
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*/
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fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_FPV2|FPEXC_INV|FPEXC_UFC|FPEXC_OFC|FPEXC_IOC));
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fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_DEX|FPEXC_FP2V|FPEXC_VV|FPEXC_TRAP_MASK));
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fpsid = fmrx(FPSID);
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orig_fpscr = fpscr = fmrx(FPSCR);
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/*
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* If we are running with inexact exceptions enabled, we need to
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* emulate the trigger instruction. Note that as we're emulating
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* the trigger instruction, we need to increment PC.
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* Check for the special VFP subarch 1 and FPSCR.IXE bit case
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*/
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if ((fpsid & FPSID_ARCH_MASK) == (1 << FPSID_ARCH_BIT)
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&& (fpscr & FPSCR_IXE)) {
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/*
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* Synchronous exception, emulate the trigger instruction
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*/
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if (fpscr & FPSCR_IXE) {
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regs->ARM_pc += 4;
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goto emulate;
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}
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barrier();
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if (fpexc & FPEXC_EX) {
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/*
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* Asynchronous exception. The instruction is read from FPINST
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* and the interrupted instruction has to be restarted.
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*/
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trigger = fmrx(FPINST);
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regs->ARM_pc -= 4;
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} else if (!(fpexc & FPEXC_DEX)) {
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/*
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* Illegal combination of bits. It can be caused by an
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* unallocated VFP instruction but with FPSCR.IXE set and not
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* on VFP subarch 1.
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*/
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vfp_raise_exceptions(VFP_EXCEPTION_ERROR, trigger, fpscr, regs);
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return;
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}
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/*
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* Modify fpscr to indicate the number of iterations remaining
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* Modify fpscr to indicate the number of iterations remaining.
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* If FPEXC.EX is 0, FPEXC.DEX is 1 and the FPEXC.VV bit indicates
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* whether FPEXC.VECITR or FPSCR.LEN is used.
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*/
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if (fpexc & FPEXC_EX) {
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if (fpexc & (FPEXC_EX | FPEXC_VV)) {
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u32 len;
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len = fpexc + (1 << FPEXC_LENGTH_BIT);
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@ -262,15 +288,15 @@ void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
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* FPEXC bounce reason, but this appears to be unreliable.
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* Emulate the bounced instruction instead.
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*/
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inst = fmrx(FPINST);
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exceptions = vfp_emulate_instruction(inst, fpscr, regs);
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exceptions = vfp_emulate_instruction(trigger, fpscr, regs);
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if (exceptions)
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vfp_raise_exceptions(exceptions, inst, orig_fpscr, regs);
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vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs);
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/*
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* If there isn't a second FP instruction, exit now.
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* If there isn't a second FP instruction, exit now. Note that
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* the FPEXC.FP2V bit is valid only if FPEXC.EX is 1.
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*/
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if (!(fpexc & FPEXC_FPV2))
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if (fpexc ^ (FPEXC_EX | FPEXC_FP2V))
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return;
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/*
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@ -279,10 +305,9 @@ void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
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*/
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barrier();
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trigger = fmrx(FPINST2);
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orig_fpscr = fpscr = fmrx(FPSCR);
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emulate:
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exceptions = vfp_emulate_instruction(trigger, fpscr, regs);
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exceptions = vfp_emulate_instruction(trigger, orig_fpscr, regs);
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if (exceptions)
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vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs);
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}
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@ -306,16 +331,9 @@ static int __init vfp_init(void)
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{
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unsigned int vfpsid;
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unsigned int cpu_arch = cpu_architecture();
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u32 access = 0;
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if (cpu_arch >= CPU_ARCH_ARMv6) {
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access = get_copro_access();
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/*
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* Enable full access to VFP (cp10 and cp11)
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*/
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set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11));
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}
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if (cpu_arch >= CPU_ARCH_ARMv6)
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vfp_enable(NULL);
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/*
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* First check that there is a VFP that we can use.
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@ -329,15 +347,9 @@ static int __init vfp_init(void)
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vfp_vector = vfp_null_entry;
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printk(KERN_INFO "VFP support v0.3: ");
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if (VFP_arch) {
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if (VFP_arch)
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printk("not present\n");
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/*
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* Restore the copro access register.
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*/
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if (cpu_arch >= CPU_ARCH_ARMv6)
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set_copro_access(access);
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} else if (vfpsid & FPSID_NODOUBLE) {
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else if (vfpsid & FPSID_NODOUBLE) {
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printk("no double precision support\n");
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} else {
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smp_call_function(vfp_enable, NULL, 1, 1);
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@ -8,6 +8,8 @@
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#define FPSID cr0
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#define FPSCR cr1
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#define FPEXC cr8
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#define FPINST cr9
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#define FPINST2 cr10
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/* FPSID bits */
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#define FPSID_IMPLEMENTER_BIT (24)
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@ -28,6 +30,19 @@
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/* FPEXC bits */
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#define FPEXC_EX (1 << 31)
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#define FPEXC_EN (1 << 30)
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#define FPEXC_DEX (1 << 29)
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#define FPEXC_FP2V (1 << 28)
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#define FPEXC_VV (1 << 27)
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#define FPEXC_TFV (1 << 26)
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#define FPEXC_LENGTH_BIT (8)
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#define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT)
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#define FPEXC_IDF (1 << 7)
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#define FPEXC_IXF (1 << 4)
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#define FPEXC_UFF (1 << 3)
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#define FPEXC_OFF (1 << 2)
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#define FPEXC_DZF (1 << 1)
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#define FPEXC_IOF (1 << 0)
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#define FPEXC_TRAP_MASK (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF)
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/* FPSCR bits */
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#define FPSCR_DEFAULT_NAN (1<<25)
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@ -55,21 +70,6 @@
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#define FPSCR_IXC (1<<4)
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#define FPSCR_IDC (1<<7)
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/*
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* VFP9-S specific.
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*/
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#define FPINST cr9
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#define FPINST2 cr10
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/* FPEXC bits */
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#define FPEXC_FPV2 (1<<28)
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#define FPEXC_LENGTH_BIT (8)
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#define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT)
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#define FPEXC_INV (1 << 7)
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#define FPEXC_UFC (1 << 3)
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#define FPEXC_OFC (1 << 2)
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#define FPEXC_IOC (1 << 0)
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/* Bit patterns for decoding the packaged operation descriptors */
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#define VFPOPDESC_LENGTH_BIT (9)
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#define VFPOPDESC_LENGTH_MASK (0x07 << VFPOPDESC_LENGTH_BIT)
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