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powerpc/fsl-booke: Enable L1 cache on e500v1/e500v2/e500mc CPUs

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Some boot loaders may not enable L1 instruction/data cache.  Check if
data and instruction caches are enabled, and enable them if needed.

Signed-off-by: Nate Case <ncase@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Nate Case 2009-06-10 15:37:28 -05:00 committed by Kumar Gala
parent c7a7a5b9a2
commit cab888e678
2 changed files with 48 additions and 3 deletions
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2
arch/powerpc/include/asm/reg_booke.h
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@ -389,12 +389,14 @@
#define ICCR_CACHE 1 /* Cacheable */ #define ICCR_CACHE 1 /* Cacheable */
/* Bit definitions for L1CSR0. */ /* Bit definitions for L1CSR0. */
#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
#define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */ #define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */
#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
#define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */ #define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */
#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
/* Bit definitions for L1CSR1. */ /* Bit definitions for L1CSR1. */
#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ #define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */
#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ #define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */

49
arch/powerpc/kernel/cpu_setup_fsl_booke.S
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@ -17,6 +17,40 @@
#include <asm/cputable.h> #include <asm/cputable.h>
#include <asm/ppc_asm.h> #include <asm/ppc_asm.h>
_GLOBAL(__e500_icache_setup)
mfspr r0, SPRN_L1CSR1
andi. r3, r0, L1CSR1_ICE
bnelr /* Already enabled */
oris r0, r0, L1CSR1_CPE@h
ori r0, r0, (L1CSR1_ICFI | L1CSR1_ICLFR | L1CSR1_ICE)
mtspr SPRN_L1CSR1, r0 /* Enable I-Cache */
isync
blr
_GLOBAL(__e500_dcache_setup)
mfspr r0, SPRN_L1CSR0
andi. r3, r0, L1CSR0_DCE
bnelr /* Already enabled */
msync
isync
li r0, 0
mtspr SPRN_L1CSR0, r0 /* Disable */
msync
isync
li r0, (L1CSR0_DCFI | L1CSR0_CLFC)
mtspr SPRN_L1CSR0, r0 /* Invalidate */
isync
1: mfspr r0, SPRN_L1CSR0
andi. r3, r0, L1CSR0_CLFC
bne+ 1b /* Wait for lock bits reset */
oris r0, r0, L1CSR0_CPE@h
ori r0, r0, L1CSR0_DCE
msync
isync
mtspr SPRN_L1CSR0, r0 /* Enable */
isync
blr
_GLOBAL(__setup_cpu_e200) _GLOBAL(__setup_cpu_e200)
/* enable dedicated debug exception handling resources (Debug APU) */ /* enable dedicated debug exception handling resources (Debug APU) */
mfspr r3,SPRN_HID0 mfspr r3,SPRN_HID0
@ -25,7 +59,16 @@ _GLOBAL(__setup_cpu_e200)
b __setup_e200_ivors b __setup_e200_ivors
_GLOBAL(__setup_cpu_e500v1) _GLOBAL(__setup_cpu_e500v1)
_GLOBAL(__setup_cpu_e500v2) _GLOBAL(__setup_cpu_e500v2)
b __setup_e500_ivors mflr r4
bl __e500_icache_setup
bl __e500_dcache_setup
bl __setup_e500_ivors
mtlr r4
blr
_GLOBAL(__setup_cpu_e500mc) _GLOBAL(__setup_cpu_e500mc)
b __setup_e500mc_ivors mflr r4
bl __e500_icache_setup
bl __e500_dcache_setup
bl __setup_e500mc_ivors
mtlr r4
blr