forked from luck/tmp_suning_uos_patched
powerpc/mm/radix: Use STD_MMU_64 to properly isolate hash related code
We also use MMU_FTR_RADIX to branch out from code path specific to hash. No functionality change. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Aneesh Kumar K.V
Michael Ellerman
parent
a8ed87c92a
commit
caca285e5a
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@ -529,7 +529,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
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std r6,PACACURRENT(r13) /* Set new 'current' */
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ld r8,KSP(r4) /* new stack pointer */
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#ifdef CONFIG_PPC_BOOK3S
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#ifdef CONFIG_PPC_STD_MMU_64
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BEGIN_MMU_FTR_SECTION
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b 2f
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_RADIX)
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BEGIN_FTR_SECTION
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clrrdi r6,r8,28 /* get its ESID */
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clrrdi r9,r1,28 /* get current sp ESID */
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@ -575,7 +578,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
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slbmte r7,r0
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isync
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2:
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#endif /* !CONFIG_PPC_BOOK3S */
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#endif /* CONFIG_PPC_STD_MMU_64 */
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CURRENT_THREAD_INFO(r7, r8) /* base of new stack */
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/* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
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@ -939,7 +939,13 @@ data_access_common:
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ld r3,PACA_EXGEN+EX_DAR(r13)
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lwz r4,PACA_EXGEN+EX_DSISR(r13)
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li r5,0x300
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std r3,_DAR(r1)
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std r4,_DSISR(r1)
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BEGIN_MMU_FTR_SECTION
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b do_hash_page /* Try to handle as hpte fault */
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MMU_FTR_SECTION_ELSE
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b handle_page_fault
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_RADIX)
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.align 7
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.globl h_data_storage_common
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@ -964,7 +970,13 @@ instruction_access_common:
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ld r3,_NIP(r1)
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andis. r4,r12,0x5820
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li r5,0x400
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std r3,_DAR(r1)
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std r4,_DSISR(r1)
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BEGIN_MMU_FTR_SECTION
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b do_hash_page /* Try to handle as hpte fault */
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MMU_FTR_SECTION_ELSE
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b handle_page_fault
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_RADIX)
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STD_EXCEPTION_COMMON(0xe20, h_instr_storage, unknown_exception)
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@ -1375,8 +1387,11 @@ slb_miss_realmode:
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stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
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std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
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#ifdef CONFIG_PPC_STD_MMU_64
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BEGIN_MMU_FTR_SECTION
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bl slb_allocate_realmode
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END_MMU_FTR_SECTION_IFCLR(MMU_FTR_RADIX)
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#endif
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/* All done -- return from exception. */
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ld r10,PACA_EXSLB+EX_LR(r13)
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@ -1384,7 +1399,9 @@ slb_miss_realmode:
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lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
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mtlr r10
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BEGIN_MMU_FTR_SECTION
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b 2f
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_RADIX)
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andi. r10,r12,MSR_RI /* check for unrecoverable exception */
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beq- 2f
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@ -1435,9 +1452,7 @@ power4_fixup_nap:
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*/
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.align 7
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do_hash_page:
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std r3,_DAR(r1)
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std r4,_DSISR(r1)
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#ifdef CONFIG_PPC_STD_MMU_64
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andis. r0,r4,0xa410 /* weird error? */
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bne- handle_page_fault /* if not, try to insert a HPTE */
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andis. r0,r4,DSISR_DABRMATCH@h
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@ -1465,6 +1480,7 @@ do_hash_page:
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/* Error */
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blt- 13f
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#endif /* CONFIG_PPC_STD_MMU_64 */
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/* Here we have a page fault that hash_page can't handle. */
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handle_page_fault:
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@ -1491,6 +1507,7 @@ handle_dabr_fault:
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12: b ret_from_except_lite
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#ifdef CONFIG_PPC_STD_MMU_64
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/* We have a page fault that hash_page could handle but HV refused
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* the PTE insertion
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*/
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@ -1500,6 +1517,7 @@ handle_dabr_fault:
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ld r4,_DAR(r1)
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bl low_hash_fault
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b ret_from_except
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#endif
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/*
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* We come here as a result of a DSI at a point where we don't want
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@ -76,6 +76,7 @@ int default_machine_kexec_prepare(struct kimage *image)
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* end of the blocked region (begin >= high). Use the
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* boolean identity !(a || b) === (!a && !b).
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*/
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#ifdef CONFIG_PPC_STD_MMU_64
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if (htab_address) {
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low = __pa(htab_address);
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high = low + htab_size_bytes;
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@ -88,6 +89,7 @@ int default_machine_kexec_prepare(struct kimage *image)
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return -ETXTBSY;
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}
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}
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#endif /* CONFIG_PPC_STD_MMU_64 */
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/* We also should not overwrite the tce tables */
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for_each_node_by_type(node, "pci") {
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@ -381,7 +383,7 @@ void default_machine_kexec(struct kimage *image)
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/* NOTREACHED */
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}
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#ifndef CONFIG_PPC_BOOK3E
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#ifdef CONFIG_PPC_STD_MMU_64
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/* Values we need to export to the second kernel via the device tree. */
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static unsigned long htab_base;
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static unsigned long htab_size;
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@ -428,4 +430,4 @@ static int __init export_htab_values(void)
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return 0;
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}
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late_initcall(export_htab_values);
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#endif /* !CONFIG_PPC_BOOK3E */
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#endif /* CONFIG_PPC_STD_MMU_64 */
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@ -80,6 +80,7 @@ void __flush_tlb_power9(unsigned int action)
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/* flush SLBs and reload */
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#ifdef CONFIG_PPC_MMU_STD_64
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static void flush_and_reload_slb(void)
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{
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struct slb_shadow *slb;
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@ -113,6 +114,7 @@ static void flush_and_reload_slb(void)
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asm volatile("slbmte %0,%1" : : "r" (rs), "r" (rb));
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}
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}
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#endif
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static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits)
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{
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@ -123,6 +125,7 @@ static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits)
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* reset the error bits whenever we handle them so that at the end
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* we can check whether we handled all of them or not.
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* */
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#ifdef CONFIG_PPC_MMU_STD_64
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if (dsisr & slb_error_bits) {
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flush_and_reload_slb();
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/* reset error bits */
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@ -134,6 +137,7 @@ static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits)
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/* reset error bits */
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dsisr &= ~P7_DSISR_MC_TLB_MULTIHIT_MFTLB;
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}
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#endif
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/* Any other errors we don't understand? */
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if (dsisr & 0xffffffffUL)
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handled = 0;
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@ -153,6 +157,7 @@ static long mce_handle_common_ierror(uint64_t srr1)
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switch (P7_SRR1_MC_IFETCH(srr1)) {
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case 0:
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break;
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#ifdef CONFIG_PPC_MMU_STD_64
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case P7_SRR1_MC_IFETCH_SLB_PARITY:
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case P7_SRR1_MC_IFETCH_SLB_MULTIHIT:
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/* flush and reload SLBs for SLB errors. */
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@ -165,6 +170,7 @@ static long mce_handle_common_ierror(uint64_t srr1)
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handled = 1;
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}
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break;
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#endif
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default:
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break;
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}
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@ -178,10 +184,12 @@ static long mce_handle_ierror_p7(uint64_t srr1)
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handled = mce_handle_common_ierror(srr1);
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#ifdef CONFIG_PPC_MMU_STD_64
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if (P7_SRR1_MC_IFETCH(srr1) == P7_SRR1_MC_IFETCH_SLB_BOTH) {
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flush_and_reload_slb();
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handled = 1;
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}
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#endif
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return handled;
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}
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@ -324,10 +332,12 @@ static long mce_handle_ierror_p8(uint64_t srr1)
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handled = mce_handle_common_ierror(srr1);
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#ifdef CONFIG_PPC_MMU_STD_64
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if (P7_SRR1_MC_IFETCH(srr1) == P8_SRR1_MC_IFETCH_ERAT_MULTIHIT) {
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flush_and_reload_slb();
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handled = 1;
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}
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#endif
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return handled;
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}
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@ -1079,7 +1079,7 @@ struct task_struct *__switch_to(struct task_struct *prev,
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}
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#endif /* CONFIG_PPC64 */
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#ifdef CONFIG_PPC_BOOK3S_64
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#ifdef CONFIG_PPC_STD_MMU_64
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batch = this_cpu_ptr(&ppc64_tlb_batch);
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if (batch->active) {
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current_thread_info()->local_flags |= _TLF_LAZY_MMU;
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@ -1087,7 +1087,7 @@ struct task_struct *__switch_to(struct task_struct *prev,
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__flush_tlb_pending(batch);
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batch->active = 0;
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}
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#endif /* CONFIG_PPC_BOOK3S_64 */
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#endif /* CONFIG_PPC_STD_MMU_64 */
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#ifdef CONFIG_PPC_ADV_DEBUG_REGS
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switch_booke_debug_regs(&new->thread.debug);
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@ -1133,7 +1133,7 @@ struct task_struct *__switch_to(struct task_struct *prev,
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last = _switch(old_thread, new_thread);
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#ifdef CONFIG_PPC_BOOK3S_64
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#ifdef CONFIG_PPC_STD_MMU_64
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if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
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current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
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batch = this_cpu_ptr(&ppc64_tlb_batch);
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@ -1142,8 +1142,7 @@ struct task_struct *__switch_to(struct task_struct *prev,
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if (current_thread_info()->task->thread.regs)
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restore_math(current_thread_info()->task->thread.regs);
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#endif /* CONFIG_PPC_BOOK3S_64 */
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#endif /* CONFIG_PPC_STD_MMU_64 */
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return last;
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}
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@ -1378,6 +1377,9 @@ static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
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unsigned long sp_vsid;
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unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
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if (radix_enabled())
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return;
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if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
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sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
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<< SLB_VSID_SHIFT_1T;
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@ -1926,7 +1928,8 @@ unsigned long arch_randomize_brk(struct mm_struct *mm)
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* the heap, we can put it above 1TB so it is backed by a 1TB
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* segment. Otherwise the heap will be in the bottom 1TB
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* which always uses 256MB segments and this may result in a
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* performance penalty.
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* performance penalty. We don't need to worry about radix. For
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* radix, mmu_highuser_ssize remains unchanged from 256MB.
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*/
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if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
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base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
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@ -2913,7 +2913,7 @@ static void xmon_print_symbol(unsigned long address, const char *mid,
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printf("%s", after);
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}
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#ifdef CONFIG_PPC_BOOK3S_64
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#ifdef CONFIG_PPC_STD_MMU_64
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void dump_segments(void)
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{
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int i;
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