forked from luck/tmp_suning_uos_patched
microblaze: Support timer on AXI lite
New microblaze systems uses two buses. One for memories and flashes and the second for low-speed peripherals which can run on different CLK. This is the reason why the kernel is trying to read clock-frequency directly from node. If there is then the kernel will work with it. If not then cpu CLK is used. Signed-off-by: Michal Simek <monstr@monstr.eu>
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02b08045a0
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ccea0e6e49
@ -77,7 +77,6 @@ struct cpuinfo {
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u32 num_rd_brk;
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u32 num_wr_brk;
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u32 cpu_clock_freq; /* store real freq of cpu */
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u32 freq_div_hz; /* store freq/HZ */
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/* FPGA family */
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u32 fpga_family_code;
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@ -38,6 +38,9 @@ static unsigned int timer_baseaddr;
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#define TIMER_BASE timer_baseaddr
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#endif
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unsigned int freq_div_hz;
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unsigned int timer_clock_freq;
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#define TCSR0 (0x00)
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#define TLR0 (0x04)
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#define TCR0 (0x08)
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@ -115,7 +118,7 @@ static void microblaze_timer_set_mode(enum clock_event_mode mode,
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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printk(KERN_INFO "%s: periodic\n", __func__);
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microblaze_timer0_start_periodic(cpuinfo.freq_div_hz);
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microblaze_timer0_start_periodic(freq_div_hz);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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printk(KERN_INFO "%s: oneshot\n", __func__);
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@ -168,7 +171,7 @@ static struct irqaction timer_irqaction = {
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static __init void microblaze_clockevent_init(void)
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{
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clockevent_microblaze_timer.mult =
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div_sc(cpuinfo.cpu_clock_freq, NSEC_PER_SEC,
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div_sc(timer_clock_freq, NSEC_PER_SEC,
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clockevent_microblaze_timer.shift);
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clockevent_microblaze_timer.max_delta_ns =
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clockevent_delta2ns((u32)~0, &clockevent_microblaze_timer);
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@ -201,7 +204,7 @@ static struct cyclecounter microblaze_cc = {
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int __init init_microblaze_timecounter(void)
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{
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microblaze_cc.mult = div_sc(cpuinfo.cpu_clock_freq, NSEC_PER_SEC,
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microblaze_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC,
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microblaze_cc.shift);
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timecounter_init(µblaze_tc, µblaze_cc, sched_clock());
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@ -221,7 +224,7 @@ static struct clocksource clocksource_microblaze = {
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static int __init microblaze_clocksource_init(void)
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{
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clocksource_microblaze.mult =
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clocksource_hz2mult(cpuinfo.cpu_clock_freq,
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clocksource_hz2mult(timer_clock_freq,
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clocksource_microblaze.shift);
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if (clocksource_register(&clocksource_microblaze))
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panic("failed to register clocksource");
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@ -247,6 +250,7 @@ void __init time_init(void)
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u32 irq, i = 0;
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u32 timer_num = 1;
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struct device_node *timer = NULL;
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const void *prop;
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#ifdef CONFIG_SELFMOD_TIMER
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unsigned int timer_baseaddr = 0;
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int arr_func[] = {
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@ -286,7 +290,14 @@ void __init time_init(void)
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printk(KERN_INFO "%s #0 at 0x%08x, irq=%d\n",
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timer_list[i], timer_baseaddr, irq);
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cpuinfo.freq_div_hz = cpuinfo.cpu_clock_freq / HZ;
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/* If there is clock-frequency property than use it */
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prop = of_get_property(timer, "clock-frequency", NULL);
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if (prop)
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timer_clock_freq = be32_to_cpup(prop);
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else
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timer_clock_freq = cpuinfo.cpu_clock_freq;
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freq_div_hz = timer_clock_freq / HZ;
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setup_irq(irq, &timer_irqaction);
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#ifdef CONFIG_HEART_BEAT
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