forked from luck/tmp_suning_uos_patched
Blackfin: switch to asm-generic/io.h
Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
efb2d31c1c
commit
cfbf1677a3
@ -1,5 +1,5 @@
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/*
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* Copyright 2004-2009 Analog Devices Inc.
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* Copyright 2004-2010 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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@ -7,148 +7,48 @@
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#ifndef _BFIN_IO_H
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#define _BFIN_IO_H
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#endif
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <asm/byteorder.h>
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/*
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* These are for ISA/PCI shared memory _only_ and should never be used
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* on any other type of memory, including Zorro memory. They are meant to
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* access the bus in the bus byte order which is little-endian!.
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*
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* readX/writeX() are used to access memory mapped devices. On some
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* architectures the memory mapped IO stuff needs to be accessed
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* differently. On the bfin architecture, we just read/write the
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* memory location directly.
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*/
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#ifndef __ASSEMBLY__
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static inline unsigned char readb(const volatile void __iomem *addr)
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{
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unsigned int val;
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int tmp;
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__asm__ __volatile__ (
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"cli %1;"
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"NOP; NOP; SSYNC;"
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"%0 = b [%2] (z);"
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"sti %1;"
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: "=d"(val), "=d"(tmp)
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: "a"(addr)
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);
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return (unsigned char) val;
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#define DECLARE_BFIN_RAW_READX(size, type, asm, asm_sign) \
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static inline type __raw_read##size(const volatile void __iomem *addr) \
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{ \
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unsigned int val; \
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int tmp; \
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__asm__ __volatile__ ( \
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"cli %1;" \
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"NOP; NOP; SSYNC;" \
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"%0 = "#asm" [%2] "#asm_sign";" \
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"sti %1;" \
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: "=d"(val), "=d"(tmp) \
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: "a"(addr) \
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); \
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return (type) val; \
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}
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static inline unsigned short readw(const volatile void __iomem *addr)
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{
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unsigned int val;
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int tmp;
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__asm__ __volatile__ (
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"cli %1;"
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"NOP; NOP; SSYNC;"
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"%0 = w [%2] (z);"
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"sti %1;"
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: "=d"(val), "=d"(tmp)
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: "a"(addr)
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);
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return (unsigned short) val;
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}
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static inline unsigned int readl(const volatile void __iomem *addr)
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{
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unsigned int val;
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int tmp;
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__asm__ __volatile__ (
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"cli %1;"
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"NOP; NOP; SSYNC;"
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"%0 = [%2];"
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"sti %1;"
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: "=d"(val), "=d"(tmp)
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: "a"(addr)
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);
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return val;
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}
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#endif /* __ASSEMBLY__ */
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#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
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#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
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#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
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#define __raw_readb readb
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#define __raw_readw readw
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#define __raw_readl readl
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#define __raw_writeb writeb
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#define __raw_writew writew
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#define __raw_writel writel
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#define memset_io(a, b, c) memset((void *)(a), (b), (c))
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#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
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#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
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/* Convert "I/O port addresses" to actual addresses. i.e. ugly casts. */
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#define __io(port) ((void *)(unsigned long)(port))
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#define inb(port) readb(__io(port))
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#define inw(port) readw(__io(port))
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#define inl(port) readl(__io(port))
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#define outb(x, port) writeb(x, __io(port))
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#define outw(x, port) writew(x, __io(port))
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#define outl(x, port) writel(x, __io(port))
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#define inb_p(port) inb(__io(port))
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#define inw_p(port) inw(__io(port))
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#define inl_p(port) inl(__io(port))
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#define outb_p(x, port) outb(x, __io(port))
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#define outw_p(x, port) outw(x, __io(port))
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#define outl_p(x, port) outl(x, __io(port))
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#define ioread8_rep(a, d, c) readsb(a, d, c)
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#define ioread16_rep(a, d, c) readsw(a, d, c)
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#define ioread32_rep(a, d, c) readsl(a, d, c)
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#define iowrite8_rep(a, s, c) writesb(a, s, c)
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#define iowrite16_rep(a, s, c) writesw(a, s, c)
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#define iowrite32_rep(a, s, c) writesl(a, s, c)
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#define ioread8(x) readb(x)
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#define ioread16(x) readw(x)
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#define ioread32(x) readl(x)
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#define iowrite8(val, x) writeb(val, x)
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#define iowrite16(val, x) writew(val, x)
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#define iowrite32(val, x) writel(val, x)
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/**
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* I/O write barrier
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*
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* Ensure ordering of I/O space writes. This will make sure that writes
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* following the barrier will arrive after all previous writes.
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*/
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#define mmiowb() do { SSYNC(); wmb(); } while (0)
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#define IO_SPACE_LIMIT 0xffffffff
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/* Values for nocacheflag and cmode */
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#define IOMAP_NOCACHE_SER 1
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#ifndef __ASSEMBLY__
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DECLARE_BFIN_RAW_READX(b, u8, b, (z))
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#define __raw_readb __raw_readb
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DECLARE_BFIN_RAW_READX(w, u16, w, (z))
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#define __raw_readw __raw_readw
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DECLARE_BFIN_RAW_READX(l, u32, , )
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#define __raw_readl __raw_readl
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extern void outsb(unsigned long port, const void *addr, unsigned long count);
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extern void outsw(unsigned long port, const void *addr, unsigned long count);
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extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
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extern void outsl(unsigned long port, const void *addr, unsigned long count);
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#define outsb outsb
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#define outsw outsw
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#define outsl outsl
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extern void insb(unsigned long port, void *addr, unsigned long count);
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extern void insw(unsigned long port, void *addr, unsigned long count);
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extern void insw_8(unsigned long port, void *addr, unsigned long count);
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extern void insl(unsigned long port, void *addr, unsigned long count);
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extern void insl_16(unsigned long port, void *addr, unsigned long count);
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#define insb insb
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#define insw insw
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#define insl insl
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extern void dma_outsb(unsigned long port, const void *addr, unsigned short count);
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extern void dma_outsw(unsigned long port, const void *addr, unsigned short count);
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@ -158,78 +58,14 @@ extern void dma_insb(unsigned long port, void *addr, unsigned short count);
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extern void dma_insw(unsigned long port, void *addr, unsigned short count);
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extern void dma_insl(unsigned long port, void *addr, unsigned short count);
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/*
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* Map some physical address range into the kernel address space.
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/**
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* I/O write barrier
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*
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* Ensure ordering of I/O space writes. This will make sure that writes
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* following the barrier will arrive after all previous writes.
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*/
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static inline void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
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int cacheflag)
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{
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return (void __iomem *)physaddr;
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}
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#define mmiowb() do { SSYNC(); wmb(); } while (0)
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/*
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* Unmap a ioremap()ed region again
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*/
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static inline void iounmap(void *addr)
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{
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}
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/*
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* __iounmap unmaps nearly everything, so be careful
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* it doesn't free currently pointer/page tables anymore but it
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* wans't used anyway and might be added later.
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*/
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static inline void __iounmap(void *addr, unsigned long size)
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{
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}
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/*
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* Set new cache mode for some kernel address space.
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* The caller must push data for that range itself, if such data may already
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* be in the cache.
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*/
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static inline void kernel_set_cachemode(void *addr, unsigned long size,
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int cmode)
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{
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}
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static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
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{
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return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
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}
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static inline void __iomem *ioremap_nocache(unsigned long physaddr,
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unsigned long size)
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{
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return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
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}
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extern void blkfin_inv_cache_all(void);
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#include <asm-generic/io.h>
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#endif
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#define ioport_map(port, nr) ((void __iomem*)(port))
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#define ioport_unmap(addr)
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/* Pages to physical address... */
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#define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT)
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#define phys_to_virt(vaddr) ((void *) (vaddr))
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#define virt_to_phys(vaddr) ((unsigned long) (vaddr))
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#define virt_to_bus virt_to_phys
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#define bus_to_virt phys_to_virt
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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* access
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*/
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#define xlate_dev_mem_ptr(p) __va(p)
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/*
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* Convert a virtual cached pointer to an uncached pointer
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*/
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#define xlate_dev_kmem_ptr(p) p
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#endif /* __KERNEL__ */
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#endif /* _BFIN_IO_H */
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