forked from luck/tmp_suning_uos_patched
clk: renesas: Updates for v4.11 (take two)
- Use CLK_IS_CRITICAL to handle critical clocks, - Add Reset Control Support for R-Car Gen2 and Gen3, and RZ/G1, - Add IIC-DVFS clocks for R-Car H3 and M3-W, - Minor cleanups. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYiw4ZAAoJEEgEtLw/Ve77TfgQAJexnyItLU6fs3X5gx6smoWQ rPYXw0tWWfYEkmHJbF/vcfgC+sh/6sMVIn4IS6HqDWd1HdOtJPYTX8CvwlsQx0Ry NrcoConiFlatEM5sNf6w0aAUkwrDxIjZMNNnShfZRkZL7s9Jlhs5UUUbBY4uYPGG kJ7qr6hUoxQQ1S3z8iz/ol++tp/A+8zN0J+zLDdxcV0SRjxh/NWOOtjno9tWXXqd 60eseC5FJNQOYV/6DXkpHsxNLsG6N2i7CVPC3SWxrijTQB1BDYAj/Pc3rD4u7Exo g2QTb8ywufWFi5ANhQX2oirewaiw6B2PoQyw7+7a/86OlTQVM7lfRb8hNnOJycqd X2YKBCNGeg4sysGURSYIDlzoq0ZDZnw7URc2+0HfeZXJjRCTmswpzRAv/wq4ILLK uAy5skI+XWKCuVk/w8lsWBo29hcu9Mm1lTsW739niJR4Kk9WQkK+JgF7x8FxzmLx 7W8Rpbiz1N1D8ajlJWo/FAMdfx0SqevLlQlhCNVjExl7szmOcsF8RPnx542oRfwe wgJLCmCc9msP6FdWWSXB5BLNgPbaCAOoPfzpn5xouOe2xj6V5Ctv5kBTLfTqs+5S 3SxsU08UZ4mxBeynjtuNwaX35KVs5Y1+FZQQD5MNxq8C2OvDx5ioWkH+YWFjOmgA 9zghcMX9FG1KNLWh+RUD =WluB -----END PGP SIGNATURE----- Merge tag 'clk-renesas-for-v4.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull Renesas clk driver updates from Geert Uytterhoeven: - Use CLK_IS_CRITICAL to handle critical clocks, - Add Reset Control Support for R-Car Gen2 and Gen3, and RZ/G1, - Add IIC-DVFS clocks for R-Car H3 and M3-W, - Minor cleanups. * tag 'clk-renesas-for-v4.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add IIC-DVFS clock clk: renesas: r8a7795: Add IIC-DVFS clock clk: renesas: cpg-mssr: Add support for reset control clk: renesas: cpg-mssr: Rename cpg_mssr_priv.mstp_lock clk: renesas: cpg-mssr: Document suitability for RZ/G1 dt-bindings: clock: renesas: cpg-mssr: Document reset control support clk: renesas: mstp: Reformat cpg_mstp_clock_register() for git diff clk: renesas: mstp: Make INTC-SYS a critical clock clk: renesas: cpg-mssr: Migrate to CLK_IS_CRITICAL
This commit is contained in:
Stephen Boyd
commit
d646d812f3
@ -42,6 +42,10 @@ Required Properties:
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Domain bindings in
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Documentation/devicetree/bindings/power/power_domain.txt.
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- #reset-cells: Must be 1
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- The single reset specifier cell must be the module number, as defined
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in the datasheet.
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Examples
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--------
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@ -55,6 +59,7 @@ Examples
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clock-names = "extal", "extalr";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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@ -69,5 +74,6 @@ Examples
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dmas = <&dmac1 0x13>, <&dmac1 0x12>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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resets = <&cpg 310>;
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status = "disabled";
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};
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@ -141,9 +141,9 @@ static const struct clk_ops cpg_mstp_clock_ops = {
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.is_enabled = cpg_mstp_clock_is_enabled,
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};
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static struct clk * __init
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cpg_mstp_clock_register(const char *name, const char *parent_name,
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unsigned int index, struct mstp_clock_group *group)
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static struct clk * __init cpg_mstp_clock_register(const char *name,
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const char *parent_name, unsigned int index,
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struct mstp_clock_group *group)
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{
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struct clk_init_data init;
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struct mstp_clock *clock;
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@ -158,6 +158,11 @@ cpg_mstp_clock_register(const char *name, const char *parent_name,
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init.name = name;
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init.ops = &cpg_mstp_clock_ops;
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init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
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/* INTC-SYS is the module clock of the GIC, and must not be disabled */
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if (!strcmp(name, "intc-sys")) {
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pr_debug("MSTP %s setting CLK_IS_CRITICAL\n", name);
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init.flags |= CLK_IS_CRITICAL;
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}
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init.parent_names = &parent_name;
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init.num_parents = 1;
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@ -221,6 +221,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
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DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
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DEF_MOD("i2c6", 918, R8A7795_CLK_S3D2),
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DEF_MOD("i2c5", 919, R8A7795_CLK_S3D2),
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DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
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DEF_MOD("i2c4", 927, R8A7795_CLK_S3D2),
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DEF_MOD("i2c3", 928, R8A7795_CLK_S3D2),
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DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
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@ -192,6 +192,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
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DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4),
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DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6),
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DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6),
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DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
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DEF_MOD("i2c4", 927, R8A7796_CLK_S0D6),
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DEF_MOD("i2c3", 928, R8A7796_CLK_S0D6),
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DEF_MOD("i2c2", 929, R8A7796_CLK_S3D2),
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@ -16,6 +16,7 @@
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/renesas.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/mod_devicetable.h>
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@ -25,6 +26,7 @@
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#include <linux/platform_device.h>
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#include <linux/pm_clock.h>
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#include <linux/pm_domain.h>
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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@ -43,7 +45,7 @@
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* Module Standby and Software Reset register offets.
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*
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* If the registers exist, these are valid for SH-Mobile, R-Mobile,
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* R-Car Gen 2, and R-Car Gen 3.
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* R-Car Gen2, R-Car Gen3, and RZ/G1.
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* These are NOT valid for R-Car Gen1 and RZ/A1!
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*/
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@ -96,18 +98,22 @@ static const u16 srcr[] = {
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/**
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* Clock Pulse Generator / Module Standby and Software Reset Private Data
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*
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* @rcdev: Optional reset controller entity
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* @dev: CPG/MSSR device
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* @base: CPG/MSSR register block base address
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* @mstp_lock: protects writes to SMSTPCR
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* @rmw_lock: protects RMW register accesses
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* @clks: Array containing all Core and Module Clocks
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* @num_core_clks: Number of Core Clocks in clks[]
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* @num_mod_clks: Number of Module Clocks in clks[]
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* @last_dt_core_clk: ID of the last Core Clock exported to DT
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*/
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struct cpg_mssr_priv {
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#ifdef CONFIG_RESET_CONTROLLER
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struct reset_controller_dev rcdev;
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#endif
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struct device *dev;
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void __iomem *base;
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spinlock_t mstp_lock;
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spinlock_t rmw_lock;
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struct clk **clks;
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unsigned int num_core_clks;
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@ -144,7 +150,7 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
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dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
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enable ? "ON" : "OFF");
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spin_lock_irqsave(&priv->mstp_lock, flags);
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spin_lock_irqsave(&priv->rmw_lock, flags);
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value = readl(priv->base + SMSTPCR(reg));
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if (enable)
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@ -153,7 +159,7 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
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value |= bitmask;
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writel(value, priv->base + SMSTPCR(reg));
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spin_unlock_irqrestore(&priv->mstp_lock, flags);
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spin_unlock_irqrestore(&priv->rmw_lock, flags);
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if (!enable)
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return 0;
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@ -346,17 +352,10 @@ static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
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init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
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for (i = 0; i < info->num_crit_mod_clks; i++)
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if (id == info->crit_mod_clks[i]) {
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#ifdef CLK_ENABLE_HAND_OFF
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dev_dbg(dev, "MSTP %s setting CLK_ENABLE_HAND_OFF\n",
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dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n",
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mod->name);
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init.flags |= CLK_ENABLE_HAND_OFF;
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init.flags |= CLK_IS_CRITICAL;
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break;
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#else
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dev_dbg(dev, "Ignoring MSTP %s to prevent disabling\n",
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mod->name);
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kfree(clock);
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return;
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#endif
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}
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parent_name = __clk_get_name(parent);
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@ -501,6 +500,122 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev,
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return 0;
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}
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#ifdef CONFIG_RESET_CONTROLLER
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#define rcdev_to_priv(x) container_of(x, struct cpg_mssr_priv, rcdev)
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static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
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unsigned int reg = id / 32;
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unsigned int bit = id % 32;
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u32 bitmask = BIT(bit);
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unsigned long flags;
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u32 value;
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dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
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/* Reset module */
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spin_lock_irqsave(&priv->rmw_lock, flags);
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value = readl(priv->base + SRCR(reg));
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value |= bitmask;
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writel(value, priv->base + SRCR(reg));
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spin_unlock_irqrestore(&priv->rmw_lock, flags);
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/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
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udelay(35);
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/* Release module from reset state */
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writel(bitmask, priv->base + SRSTCLR(reg));
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return 0;
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}
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static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
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{
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struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
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unsigned int reg = id / 32;
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unsigned int bit = id % 32;
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u32 bitmask = BIT(bit);
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unsigned long flags;
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u32 value;
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dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
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spin_lock_irqsave(&priv->rmw_lock, flags);
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value = readl(priv->base + SRCR(reg));
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value |= bitmask;
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writel(value, priv->base + SRCR(reg));
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spin_unlock_irqrestore(&priv->rmw_lock, flags);
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return 0;
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}
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static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
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unsigned int reg = id / 32;
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unsigned int bit = id % 32;
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u32 bitmask = BIT(bit);
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dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
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writel(bitmask, priv->base + SRSTCLR(reg));
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return 0;
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}
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static int cpg_mssr_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
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unsigned int reg = id / 32;
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unsigned int bit = id % 32;
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u32 bitmask = BIT(bit);
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return !!(readl(priv->base + SRCR(reg)) & bitmask);
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}
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static const struct reset_control_ops cpg_mssr_reset_ops = {
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.reset = cpg_mssr_reset,
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.assert = cpg_mssr_assert,
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.deassert = cpg_mssr_deassert,
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.status = cpg_mssr_status,
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};
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static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev,
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const struct of_phandle_args *reset_spec)
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{
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struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
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unsigned int unpacked = reset_spec->args[0];
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unsigned int idx = MOD_CLK_PACK(unpacked);
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if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) {
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dev_err(priv->dev, "Invalid reset index %u\n", unpacked);
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return -EINVAL;
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}
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return idx;
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}
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static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
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{
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priv->rcdev.ops = &cpg_mssr_reset_ops;
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priv->rcdev.of_node = priv->dev->of_node;
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priv->rcdev.of_reset_n_cells = 1;
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priv->rcdev.of_xlate = cpg_mssr_reset_xlate;
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priv->rcdev.nr_resets = priv->num_mod_clks;
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return devm_reset_controller_register(priv->dev, &priv->rcdev);
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}
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#else /* !CONFIG_RESET_CONTROLLER */
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static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
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{
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return 0;
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}
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#endif /* !CONFIG_RESET_CONTROLLER */
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static const struct of_device_id cpg_mssr_match[] = {
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#ifdef CONFIG_ARCH_R8A7743
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{
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@ -557,7 +672,7 @@ static int __init cpg_mssr_probe(struct platform_device *pdev)
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return -ENOMEM;
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priv->dev = dev;
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spin_lock_init(&priv->mstp_lock);
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spin_lock_init(&priv->rmw_lock);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->base = devm_ioremap_resource(dev, res);
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@ -598,6 +713,10 @@ static int __init cpg_mssr_probe(struct platform_device *pdev)
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if (error)
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return error;
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error = cpg_mssr_reset_controller_register(priv);
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if (error)
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return error;
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return 0;
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}
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