forked from luck/tmp_suning_uos_patched
pinctrl: aspeed-g6: Rename SD3 to EMMC and rework pin groups
AST2600 EMMC support 3 types DAT bus sizes (1, 4 and 8-bit),
corresponding to 3 groups: EMMCG1, EMMCG4 and EMMCG8
Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support")
Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20191008044153.12734-8-andrew@aj.id.au
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Johnny Huang
Linus Walleij
parent
1550583432
commit
d6e7a1a511
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@ -1440,74 +1440,72 @@ FUNC_GROUP_DECL(RGMII2, D4, C2, C1, D3, E4, F5, D2, E3, D1, F4, E2, E1);
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FUNC_GROUP_DECL(RMII2, D4, C2, C1, D3, D2, D1, F4, E2, E1);
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#define AB4 232
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SIG_EXPR_LIST_DECL_SESG(AB4, SD3CLK, SD3, SIG_DESC_SET(SCU400, 24));
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PIN_DECL_1(AB4, GPIO18D0, SD3CLK);
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SIG_EXPR_LIST_DECL_SEMG(AB4, EMMCCLK, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 24));
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PIN_DECL_1(AB4, GPIO18D0, EMMCCLK);
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#define AA4 233
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SIG_EXPR_LIST_DECL_SESG(AA4, SD3CMD, SD3, SIG_DESC_SET(SCU400, 25));
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PIN_DECL_1(AA4, GPIO18D1, SD3CMD);
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SIG_EXPR_LIST_DECL_SEMG(AA4, EMMCCMD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 25));
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PIN_DECL_1(AA4, GPIO18D1, EMMCCMD);
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#define AC4 234
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SIG_EXPR_LIST_DECL_SESG(AC4, SD3DAT0, SD3, SIG_DESC_SET(SCU400, 26));
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PIN_DECL_1(AC4, GPIO18D2, SD3DAT0);
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SIG_EXPR_LIST_DECL_SEMG(AC4, EMMCDAT0, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 26));
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PIN_DECL_1(AC4, GPIO18D2, EMMCDAT0);
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#define AA5 235
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SIG_EXPR_LIST_DECL_SESG(AA5, SD3DAT1, SD3, SIG_DESC_SET(SCU400, 27));
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PIN_DECL_1(AA5, GPIO18D3, SD3DAT1);
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SIG_EXPR_LIST_DECL_SEMG(AA5, EMMCDAT1, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 27));
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PIN_DECL_1(AA5, GPIO18D3, EMMCDAT1);
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#define Y5 236
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SIG_EXPR_LIST_DECL_SESG(Y5, SD3DAT2, SD3, SIG_DESC_SET(SCU400, 28));
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PIN_DECL_1(Y5, GPIO18D4, SD3DAT2);
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SIG_EXPR_LIST_DECL_SEMG(Y5, EMMCDAT2, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 28));
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PIN_DECL_1(Y5, GPIO18D4, EMMCDAT2);
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#define AB5 237
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SIG_EXPR_LIST_DECL_SESG(AB5, SD3DAT3, SD3, SIG_DESC_SET(SCU400, 29));
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PIN_DECL_1(AB5, GPIO18D5, SD3DAT3);
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SIG_EXPR_LIST_DECL_SEMG(AB5, EMMCDAT3, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 29));
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PIN_DECL_1(AB5, GPIO18D5, EMMCDAT3);
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#define AB6 238
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SIG_EXPR_LIST_DECL_SESG(AB6, SD3CD, SD3, SIG_DESC_SET(SCU400, 30));
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PIN_DECL_1(AB6, GPIO18D6, SD3CD);
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SIG_EXPR_LIST_DECL_SEMG(AB6, EMMCCD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 30));
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PIN_DECL_1(AB6, GPIO18D6, EMMCCD);
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#define AC5 239
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SIG_EXPR_LIST_DECL_SESG(AC5, SD3WP, SD3, SIG_DESC_SET(SCU400, 31));
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PIN_DECL_1(AC5, GPIO18D7, SD3WP);
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SIG_EXPR_LIST_DECL_SEMG(AC5, EMMCWP, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 31));
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PIN_DECL_1(AC5, GPIO18D7, EMMCWP);
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FUNC_GROUP_DECL(SD3, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5);
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GROUP_DECL(EMMCG1, AB4, AA4, AC4, AB6, AC5);
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GROUP_DECL(EMMCG4, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5);
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#define Y1 240
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SIG_EXPR_LIST_DECL_SEMG(Y1, FWSPIDCS, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3));
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SIG_EXPR_LIST_DECL_SESG(Y1, VBCS, VB, SIG_DESC_SET(SCU500, 5));
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SIG_EXPR_LIST_DECL_SESG(Y1, SD3DAT4, SD3DAT4, SIG_DESC_SET(SCU404, 0));
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PIN_DECL_3(Y1, GPIO18E0, FWSPIDCS, VBCS, SD3DAT4);
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FUNC_GROUP_DECL(SD3DAT4, Y1);
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SIG_EXPR_LIST_DECL_SEMG(Y1, EMMCDAT4, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 0));
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PIN_DECL_3(Y1, GPIO18E0, FWSPIDCS, VBCS, EMMCDAT4);
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#define Y2 241
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SIG_EXPR_LIST_DECL_SEMG(Y2, FWSPIDCK, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3));
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SIG_EXPR_LIST_DECL_SESG(Y2, VBCK, VB, SIG_DESC_SET(SCU500, 5));
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SIG_EXPR_LIST_DECL_SESG(Y2, SD3DAT5, SD3DAT5, SIG_DESC_SET(SCU404, 1));
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PIN_DECL_3(Y2, GPIO18E1, FWSPIDCK, VBCK, SD3DAT5);
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FUNC_GROUP_DECL(SD3DAT5, Y2);
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SIG_EXPR_LIST_DECL_SEMG(Y2, EMMCDAT5, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 1));
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PIN_DECL_3(Y2, GPIO18E1, FWSPIDCK, VBCK, EMMCDAT5);
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#define Y3 242
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SIG_EXPR_LIST_DECL_SEMG(Y3, FWSPIDMOSI, FWSPID, FWSPID,
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SIG_DESC_SET(SCU500, 3));
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SIG_EXPR_LIST_DECL_SESG(Y3, VBMOSI, VB, SIG_DESC_SET(SCU500, 5));
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SIG_EXPR_LIST_DECL_SESG(Y3, SD3DAT6, SD3DAT6, SIG_DESC_SET(SCU404, 2));
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PIN_DECL_3(Y3, GPIO18E2, FWSPIDMOSI, VBMOSI, SD3DAT6);
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FUNC_GROUP_DECL(SD3DAT6, Y3);
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SIG_EXPR_LIST_DECL_SEMG(Y3, EMMCDAT6, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 2));
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PIN_DECL_3(Y3, GPIO18E2, FWSPIDMOSI, VBMOSI, EMMCDAT6);
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#define Y4 243
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SIG_EXPR_LIST_DECL_SEMG(Y4, FWSPIDMISO, FWSPID, FWSPID,
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SIG_DESC_SET(SCU500, 3));
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SIG_EXPR_LIST_DECL_SESG(Y4, VBMISO, VB, SIG_DESC_SET(SCU500, 5));
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SIG_EXPR_LIST_DECL_SESG(Y4, SD3DAT7, SD3DAT7, SIG_DESC_SET(SCU404, 3));
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PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, SD3DAT7);
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FUNC_GROUP_DECL(SD3DAT7, Y4);
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SIG_EXPR_LIST_DECL_SEMG(Y4, EMMCDAT7, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 3));
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PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, EMMCDAT7);
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GROUP_DECL(FWSPID, Y1, Y2, Y3, Y4);
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GROUP_DECL(FWQSPID, Y1, Y2, Y3, Y4, AE12, AF12);
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GROUP_DECL(EMMCG8, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5, Y1, Y2, Y3, Y4);
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FUNC_DECL_2(FWSPID, FWSPID, FWQSPID);
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FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4);
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FUNC_DECL_3(EMMC, EMMCG1, EMMCG4, EMMCG8);
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/*
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* FIXME: Confirm bits and priorities are the right way around for the
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* following 4 pins
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@ -1968,11 +1966,9 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = {
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ASPEED_PINCTRL_GROUP(SALT9G1),
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ASPEED_PINCTRL_GROUP(SD1),
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ASPEED_PINCTRL_GROUP(SD2),
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ASPEED_PINCTRL_GROUP(SD3),
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ASPEED_PINCTRL_GROUP(SD3DAT4),
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ASPEED_PINCTRL_GROUP(SD3DAT5),
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ASPEED_PINCTRL_GROUP(SD3DAT6),
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ASPEED_PINCTRL_GROUP(SD3DAT7),
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ASPEED_PINCTRL_GROUP(EMMCG1),
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ASPEED_PINCTRL_GROUP(EMMCG4),
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ASPEED_PINCTRL_GROUP(EMMCG8),
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ASPEED_PINCTRL_GROUP(SGPM1),
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ASPEED_PINCTRL_GROUP(SGPS1),
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ASPEED_PINCTRL_GROUP(SIOONCTRL),
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@ -2051,6 +2047,7 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = {
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ASPEED_PINCTRL_FUNC(ADC8),
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ASPEED_PINCTRL_FUNC(ADC9),
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ASPEED_PINCTRL_FUNC(BMCINT),
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ASPEED_PINCTRL_FUNC(EMMC),
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ASPEED_PINCTRL_FUNC(ESPI),
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ASPEED_PINCTRL_FUNC(ESPIALT),
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ASPEED_PINCTRL_FUNC(FSI1),
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@ -2183,11 +2180,6 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = {
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ASPEED_PINCTRL_FUNC(SALT9),
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ASPEED_PINCTRL_FUNC(SD1),
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ASPEED_PINCTRL_FUNC(SD2),
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ASPEED_PINCTRL_FUNC(SD3),
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ASPEED_PINCTRL_FUNC(SD3DAT4),
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ASPEED_PINCTRL_FUNC(SD3DAT5),
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ASPEED_PINCTRL_FUNC(SD3DAT6),
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ASPEED_PINCTRL_FUNC(SD3DAT7),
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ASPEED_PINCTRL_FUNC(SGPM1),
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ASPEED_PINCTRL_FUNC(SGPS1),
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ASPEED_PINCTRL_FUNC(SIOONCTRL),
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@ -738,6 +738,7 @@ struct aspeed_pin_desc {
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static const char *FUNC_SYM(func)[] = { __VA_ARGS__ }
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#define FUNC_DECL_2(func, one, two) FUNC_DECL_(func, #one, #two)
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#define FUNC_DECL_3(func, one, two, three) FUNC_DECL_(func, #one, #two, #three)
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#define FUNC_GROUP_DECL(func, ...) \
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GROUP_DECL(func, __VA_ARGS__); \
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