forked from luck/tmp_suning_uos_patched
drm: update radeon to 1.25 add r200 vertex program support
Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, and new packet type for making it possible to address whole tcl vector space and have a larger count) From: Roland Scheidegger (DRM CVS) Signed-off-by: Dave Airlie <airlied@linux.ie>
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@ -161,7 +161,8 @@
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#define R200_EMIT_PP_TXCTLALL_3 91
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#define R200_EMIT_PP_TXCTLALL_4 92
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#define R200_EMIT_PP_TXCTLALL_5 93
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#define RADEON_MAX_STATE_PACKETS 94
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#define R200_EMIT_VAP_PVS_CNTL 94
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#define RADEON_MAX_STATE_PACKETS 95
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/* Commands understood by cmd_buffer ioctl. More can be added but
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* obviously these can't be removed or changed:
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@ -176,6 +177,7 @@
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#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
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* doesn't make the cpu wait, just
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* the graphics hardware */
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#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */
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typedef union {
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int i;
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@ -191,6 +193,9 @@ typedef union {
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struct {
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unsigned char cmd_type, offset, stride, count;
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} vectors;
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struct {
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unsigned char cmd_type, addr_lo, addr_hi, count;
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} veclinear;
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struct {
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unsigned char cmd_type, buf_idx, pad0, pad1;
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} dma;
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@ -38,7 +38,7 @@
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#define DRIVER_NAME "radeon"
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#define DRIVER_DESC "ATI Radeon"
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#define DRIVER_DATE "20060519"
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#define DRIVER_DATE "20060524"
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/* Interface history:
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*
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@ -93,9 +93,11 @@
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* 1.22- Add support for texture cache flushes (R300_TX_CNTL)
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* 1.23- Add new radeon memory map work from benh
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* 1.24- Add general-purpose packet for manipulating scratch registers (r300)
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* 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
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* new packet type)
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*/
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#define DRIVER_MAJOR 1
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#define DRIVER_MINOR 24
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#define DRIVER_MINOR 25
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#define DRIVER_PATCHLEVEL 0
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/*
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@ -907,6 +909,8 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
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#define R200_PP_AFS_0 0x2f80
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#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
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#define R200_VAP_PVS_CNTL_1 0x22D0
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/* Constants */
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#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
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@ -249,6 +249,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
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case R200_EMIT_PP_TXCTLALL_3:
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case R200_EMIT_PP_TXCTLALL_4:
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case R200_EMIT_PP_TXCTLALL_5:
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case R200_EMIT_VAP_PVS_CNTL:
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/* These packets don't contain memory offsets */
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break;
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@ -626,6 +627,7 @@ static struct {
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{R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
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{R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
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{R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
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{R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
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};
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/* ================================================================
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@ -2608,6 +2610,32 @@ static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv,
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return 0;
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}
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static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv,
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drm_radeon_cmd_header_t header,
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drm_radeon_kcmd_buffer_t *cmdbuf)
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{
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int sz = header.veclinear.count * 4;
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int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8);
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RING_LOCALS;
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if (!sz)
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return 0;
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if (sz * 4 > cmdbuf->bufsz)
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return DRM_ERR(EINVAL);
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BEGIN_RING(5 + sz);
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OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
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OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
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OUT_RING(start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
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OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
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OUT_RING_TABLE(cmdbuf->buf, sz);
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ADVANCE_RING();
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cmdbuf->buf += sz * sizeof(int);
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cmdbuf->bufsz -= sz * sizeof(int);
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return 0;
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}
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static int radeon_emit_packet3(drm_device_t * dev,
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drm_file_t * filp_priv,
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drm_radeon_kcmd_buffer_t *cmdbuf)
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@ -2866,6 +2894,14 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS)
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goto err;
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}
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break;
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case RADEON_CMD_VECLINEAR:
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DRM_DEBUG("RADEON_CMD_VECLINEAR\n");
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if (radeon_emit_veclinear(dev_priv, header, &cmdbuf)) {
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DRM_ERROR("radeon_emit_veclinear failed\n");
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goto err;
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}
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break;
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default:
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DRM_ERROR("bad cmd_type %d at %p\n",
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header.header.cmd_type,
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