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mlxsw: reg: Add QoS Port DSCP to Priority Mapping Register

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Add QPDP. This register controls the port default Switch Priority and
Color. The default Switch Priority and Color are used for frames where the
trust state uses default values. Currently there are two cases where this
applies: a port is in trust-PCP state, but a packet arrives untagged; and a
port is in trust-DSCP state, but a non-IP packet arrives.

Signed-off-by: Petr Machata <petrm@mellanox.com>
Acked-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Petr Machata 2019-12-29 13:48:27 +02:00 committed by David S. Miller
parent c9a2069b1d
commit d8446884f8
1 changed files with 33 additions and 0 deletions
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33
drivers/net/ethernet/mellanox/mlxsw/reg.h
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@ -3748,6 +3748,38 @@ mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)
mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp);
}
/* QPDP - QoS Port DSCP to Priority Mapping Register
* -------------------------------------------------
* This register controls the port default Switch Priority and Color. The
* default Switch Priority and Color are used for frames where the trust state
* uses default values. All member ports of a LAG should be configured with the
* same default values.
*/
#define MLXSW_REG_QPDP_ID 0x4007
#define MLXSW_REG_QPDP_LEN 0x8
MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN);
/* reg_qpdp_local_port
* Local Port. Supported for data packets from CPU port.
* Access: Index
*/
MLXSW_ITEM32(reg, qpdp, local_port, 0x00, 16, 8);
/* reg_qpdp_switch_prio
* Default port Switch Priority (default 0)
* Access: RW
*/
MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4);
static inline void mlxsw_reg_qpdp_pack(char *payload, u8 local_port,
u8 switch_prio)
{
MLXSW_REG_ZERO(qpdp, payload);
mlxsw_reg_qpdp_local_port_set(payload, local_port);
mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio);
}
/* QPDPM - QoS Port DSCP to Priority Mapping Register
* --------------------------------------------------
* This register controls the mapping from DSCP field to
@ -10580,6 +10612,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
MLXSW_REG(qeec),
MLXSW_REG(qrwe),
MLXSW_REG(qpdsm),
MLXSW_REG(qpdp),
MLXSW_REG(qpdpm),
MLXSW_REG(qtctm),
MLXSW_REG(qpsc),