forked from luck/tmp_suning_uos_patched
dmaengine: sh: Add Support SuperH DMA Engine driver
This supported all DMA channels, and it was tested in SH7722, SH7780, SH7785 and SH7763. This can not use with SH DMA API. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Reviewed-by: Matt Fleming <matt@console-pimps.org> Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Nobuhiro Iwamatsu
Dan Williams
parent
9134d02bc0
commit
d8902adcc1
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@ -1,12 +1,9 @@
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menu "DMA support"
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config SH_DMA_API
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bool
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config SH_DMA
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bool "SuperH on-chip DMA controller (DMAC) support"
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depends on CPU_SH3 || CPU_SH4
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select SH_DMA_API
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default n
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config SH_DMA_IRQ_MULTI
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@ -19,6 +16,15 @@ config SH_DMA_IRQ_MULTI
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CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || \
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CPU_SUBTYPE_SH7760
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config SH_DMA_API
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depends on SH_DMA
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bool "SuperH DMA API support"
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default n
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help
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SH_DMA_API always enabled DMA API of used SuperH.
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If you want to use DMA ENGINE, you must not enable this.
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Please enable DMA_ENGINE and SH_DMAE.
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config NR_ONCHIP_DMA_CHANNELS
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int
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depends on SH_DMA
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@ -2,8 +2,7 @@
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# Makefile for the SuperH DMA specific kernel interface routines under Linux.
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#
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obj-$(CONFIG_SH_DMA_API) += dma-api.o dma-sysfs.o
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obj-$(CONFIG_SH_DMA) += dma-sh.o
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obj-$(CONFIG_SH_DMA_API) += dma-sh.o dma-api.o dma-sysfs.o
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obj-$(CONFIG_PVR2_DMA) += dma-pvr2.o
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obj-$(CONFIG_G2_DMA) += dma-g2.o
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obj-$(CONFIG_SH_DMABRG) += dmabrg.o
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@ -115,4 +115,17 @@ static u32 dma_base_addr[] __maybe_unused = {
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#define CHCR 0x0C
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#define DMAOR 0x40
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/*
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* for dma engine
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*
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* SuperH DMA mode
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*/
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#define SHDMA_MIX_IRQ (1 << 1)
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#define SHDMA_DMAOR1 (1 << 2)
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#define SHDMA_DMAE1 (1 << 3)
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struct sh_dmae_pdata {
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unsigned int mode;
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};
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#endif /* __DMA_SH_H */
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@ -101,6 +101,14 @@ config TXX9_DMAC
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Support the TXx9 SoC internal DMA controller. This can be
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integrated in chips such as the Toshiba TX4927/38/39.
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config SH_DMAE
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tristate "Renesas SuperH DMAC support"
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depends on SUPERH && SH_DMA
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depends on !SH_DMA_API
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select DMA_ENGINE
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help
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Enable support for the Renesas SuperH DMA controllers.
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config DMA_ENGINE
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bool
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@ -9,3 +9,4 @@ obj-$(CONFIG_DW_DMAC) += dw_dmac.o
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obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
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obj-$(CONFIG_MX3_IPU) += ipu/
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obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
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obj-$(CONFIG_SH_DMAE) += shdma.o
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786
drivers/dma/shdma.c
Normal file
786
drivers/dma/shdma.c
Normal file
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@ -0,0 +1,786 @@
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/*
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* Renesas SuperH DMA Engine support
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*
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* base is drivers/dma/flsdma.c
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*
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* Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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* Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
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* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* - DMA of SuperH does not have Hardware DMA chain mode.
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* - MAX DMA size is 16MB.
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/dmaengine.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmapool.h>
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#include <linux/platform_device.h>
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#include <cpu/dma.h>
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#include <asm/dma-sh.h>
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#include "shdma.h"
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/* DMA descriptor control */
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#define DESC_LAST (-1)
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#define DESC_COMP (1)
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#define DESC_NCOMP (0)
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#define NR_DESCS_PER_CHANNEL 32
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/*
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* Define the default configuration for dual address memory-memory transfer.
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* The 0x400 value represents auto-request, external->external.
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*
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* And this driver set 4byte burst mode.
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* If you want to change mode, you need to change RS_DEFAULT of value.
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* (ex 1byte burst mode -> (RS_DUAL & ~TS_32)
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*/
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#define RS_DEFAULT (RS_DUAL)
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#define SH_DMAC_CHAN_BASE(id) (dma_base_addr[id])
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static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
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{
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ctrl_outl(data, (SH_DMAC_CHAN_BASE(sh_dc->id) + reg));
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}
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static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
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{
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return ctrl_inl((SH_DMAC_CHAN_BASE(sh_dc->id) + reg));
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}
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static void dmae_init(struct sh_dmae_chan *sh_chan)
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{
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u32 chcr = RS_DEFAULT; /* default is DUAL mode */
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sh_dmae_writel(sh_chan, chcr, CHCR);
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}
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/*
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* Reset DMA controller
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*
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* SH7780 has two DMAOR register
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*/
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static void sh_dmae_ctl_stop(int id)
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{
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unsigned short dmaor = dmaor_read_reg(id);
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dmaor &= ~(DMAOR_NMIF | DMAOR_AE);
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dmaor_write_reg(id, dmaor);
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}
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static int sh_dmae_rst(int id)
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{
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unsigned short dmaor;
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sh_dmae_ctl_stop(id);
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dmaor = (dmaor_read_reg(id)|DMAOR_INIT);
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dmaor_write_reg(id, dmaor);
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if ((dmaor_read_reg(id) & (DMAOR_AE | DMAOR_NMIF))) {
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pr_warning(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
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return -EINVAL;
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}
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return 0;
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}
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static int dmae_is_idle(struct sh_dmae_chan *sh_chan)
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{
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u32 chcr = sh_dmae_readl(sh_chan, CHCR);
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if (chcr & CHCR_DE) {
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if (!(chcr & CHCR_TE))
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return -EBUSY; /* working */
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}
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return 0; /* waiting */
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}
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static inline unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan)
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{
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u32 chcr = sh_dmae_readl(sh_chan, CHCR);
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return ts_shift[(chcr & CHCR_TS_MASK) >> CHCR_TS_SHIFT];
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}
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static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs hw)
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{
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sh_dmae_writel(sh_chan, hw.sar, SAR);
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sh_dmae_writel(sh_chan, hw.dar, DAR);
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sh_dmae_writel(sh_chan,
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(hw.tcr >> calc_xmit_shift(sh_chan)), TCR);
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}
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static void dmae_start(struct sh_dmae_chan *sh_chan)
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{
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u32 chcr = sh_dmae_readl(sh_chan, CHCR);
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chcr |= (CHCR_DE|CHCR_IE);
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sh_dmae_writel(sh_chan, chcr, CHCR);
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}
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static void dmae_halt(struct sh_dmae_chan *sh_chan)
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{
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u32 chcr = sh_dmae_readl(sh_chan, CHCR);
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chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
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sh_dmae_writel(sh_chan, chcr, CHCR);
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}
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static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
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{
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int ret = dmae_is_idle(sh_chan);
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/* When DMA was working, can not set data to CHCR */
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if (ret)
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return ret;
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sh_dmae_writel(sh_chan, val, CHCR);
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return 0;
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}
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#define DMARS1_ADDR 0x04
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#define DMARS2_ADDR 0x08
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#define DMARS_SHIFT 8
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#define DMARS_CHAN_MSK 0x01
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static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
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{
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u32 addr;
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int shift = 0;
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int ret = dmae_is_idle(sh_chan);
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if (ret)
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return ret;
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if (sh_chan->id & DMARS_CHAN_MSK)
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shift = DMARS_SHIFT;
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switch (sh_chan->id) {
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/* DMARS0 */
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case 0:
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case 1:
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addr = SH_DMARS_BASE;
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break;
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/* DMARS1 */
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case 2:
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case 3:
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addr = (SH_DMARS_BASE + DMARS1_ADDR);
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break;
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/* DMARS2 */
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case 4:
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case 5:
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addr = (SH_DMARS_BASE + DMARS2_ADDR);
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break;
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default:
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return -EINVAL;
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}
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ctrl_outw((val << shift) |
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(ctrl_inw(addr) & (shift ? 0xFF00 : 0x00FF)),
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addr);
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return 0;
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}
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static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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struct sh_desc *desc = tx_to_sh_desc(tx);
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struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan);
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dma_cookie_t cookie;
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spin_lock_bh(&sh_chan->desc_lock);
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cookie = sh_chan->common.cookie;
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cookie++;
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if (cookie < 0)
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cookie = 1;
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/* If desc only in the case of 1 */
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if (desc->async_tx.cookie != -EBUSY)
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desc->async_tx.cookie = cookie;
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sh_chan->common.cookie = desc->async_tx.cookie;
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list_splice_init(&desc->tx_list, sh_chan->ld_queue.prev);
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spin_unlock_bh(&sh_chan->desc_lock);
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return cookie;
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}
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static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan)
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{
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struct sh_desc *desc, *_desc, *ret = NULL;
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spin_lock_bh(&sh_chan->desc_lock);
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list_for_each_entry_safe(desc, _desc, &sh_chan->ld_free, node) {
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if (async_tx_test_ack(&desc->async_tx)) {
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list_del(&desc->node);
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ret = desc;
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break;
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}
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}
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spin_unlock_bh(&sh_chan->desc_lock);
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return ret;
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}
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static void sh_dmae_put_desc(struct sh_dmae_chan *sh_chan, struct sh_desc *desc)
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{
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if (desc) {
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spin_lock_bh(&sh_chan->desc_lock);
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list_splice_init(&desc->tx_list, &sh_chan->ld_free);
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list_add(&desc->node, &sh_chan->ld_free);
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spin_unlock_bh(&sh_chan->desc_lock);
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}
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}
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static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
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{
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struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
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struct sh_desc *desc;
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spin_lock_bh(&sh_chan->desc_lock);
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while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) {
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spin_unlock_bh(&sh_chan->desc_lock);
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desc = kzalloc(sizeof(struct sh_desc), GFP_KERNEL);
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if (!desc) {
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spin_lock_bh(&sh_chan->desc_lock);
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break;
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}
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dma_async_tx_descriptor_init(&desc->async_tx,
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&sh_chan->common);
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desc->async_tx.tx_submit = sh_dmae_tx_submit;
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desc->async_tx.flags = DMA_CTRL_ACK;
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INIT_LIST_HEAD(&desc->tx_list);
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sh_dmae_put_desc(sh_chan, desc);
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spin_lock_bh(&sh_chan->desc_lock);
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sh_chan->descs_allocated++;
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}
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spin_unlock_bh(&sh_chan->desc_lock);
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return sh_chan->descs_allocated;
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}
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/*
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* sh_dma_free_chan_resources - Free all resources of the channel.
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*/
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static void sh_dmae_free_chan_resources(struct dma_chan *chan)
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{
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struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
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struct sh_desc *desc, *_desc;
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LIST_HEAD(list);
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BUG_ON(!list_empty(&sh_chan->ld_queue));
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spin_lock_bh(&sh_chan->desc_lock);
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list_splice_init(&sh_chan->ld_free, &list);
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sh_chan->descs_allocated = 0;
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spin_unlock_bh(&sh_chan->desc_lock);
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list_for_each_entry_safe(desc, _desc, &list, node)
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kfree(desc);
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}
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static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
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struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
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size_t len, unsigned long flags)
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{
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struct sh_dmae_chan *sh_chan;
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struct sh_desc *first = NULL, *prev = NULL, *new;
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size_t copy_size;
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if (!chan)
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return NULL;
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if (!len)
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return NULL;
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sh_chan = to_sh_chan(chan);
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do {
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/* Allocate the link descriptor from DMA pool */
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new = sh_dmae_get_desc(sh_chan);
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if (!new) {
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dev_err(sh_chan->dev,
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"No free memory for link descriptor\n");
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goto err_get_desc;
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}
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copy_size = min(len, (size_t)SH_DMA_TCR_MAX);
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new->hw.sar = dma_src;
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new->hw.dar = dma_dest;
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new->hw.tcr = copy_size;
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if (!first)
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first = new;
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new->mark = DESC_NCOMP;
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async_tx_ack(&new->async_tx);
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prev = new;
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len -= copy_size;
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dma_src += copy_size;
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dma_dest += copy_size;
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/* Insert the link descriptor to the LD ring */
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list_add_tail(&new->node, &first->tx_list);
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} while (len);
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new->async_tx.flags = flags; /* client is in control of this ack */
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new->async_tx.cookie = -EBUSY; /* Last desc */
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return &first->async_tx;
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err_get_desc:
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sh_dmae_put_desc(sh_chan, first);
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return NULL;
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}
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/*
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* sh_chan_ld_cleanup - Clean up link descriptors
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*
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* This function clean up the ld_queue of DMA channel.
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*/
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static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan)
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{
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struct sh_desc *desc, *_desc;
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spin_lock_bh(&sh_chan->desc_lock);
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list_for_each_entry_safe(desc, _desc, &sh_chan->ld_queue, node) {
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dma_async_tx_callback callback;
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void *callback_param;
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/* non send data */
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if (desc->mark == DESC_NCOMP)
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break;
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/* send data sesc */
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callback = desc->async_tx.callback;
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callback_param = desc->async_tx.callback_param;
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/* Remove from ld_queue list */
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list_splice_init(&desc->tx_list, &sh_chan->ld_free);
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dev_dbg(sh_chan->dev, "link descriptor %p will be recycle.\n",
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desc);
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list_move(&desc->node, &sh_chan->ld_free);
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/* Run the link descriptor callback function */
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if (callback) {
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spin_unlock_bh(&sh_chan->desc_lock);
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dev_dbg(sh_chan->dev, "link descriptor %p callback\n",
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desc);
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callback(callback_param);
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spin_lock_bh(&sh_chan->desc_lock);
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}
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}
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||||
spin_unlock_bh(&sh_chan->desc_lock);
|
||||
}
|
||||
|
||||
static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
|
||||
{
|
||||
struct list_head *ld_node;
|
||||
struct sh_dmae_regs hw;
|
||||
|
||||
/* DMA work check */
|
||||
if (dmae_is_idle(sh_chan))
|
||||
return;
|
||||
|
||||
/* Find the first un-transfer desciptor */
|
||||
for (ld_node = sh_chan->ld_queue.next;
|
||||
(ld_node != &sh_chan->ld_queue)
|
||||
&& (to_sh_desc(ld_node)->mark == DESC_COMP);
|
||||
ld_node = ld_node->next)
|
||||
cpu_relax();
|
||||
|
||||
if (ld_node != &sh_chan->ld_queue) {
|
||||
/* Get the ld start address from ld_queue */
|
||||
hw = to_sh_desc(ld_node)->hw;
|
||||
dmae_set_reg(sh_chan, hw);
|
||||
dmae_start(sh_chan);
|
||||
}
|
||||
}
|
||||
|
||||
static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan)
|
||||
{
|
||||
struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
|
||||
sh_chan_xfer_ld_queue(sh_chan);
|
||||
}
|
||||
|
||||
static enum dma_status sh_dmae_is_complete(struct dma_chan *chan,
|
||||
dma_cookie_t cookie,
|
||||
dma_cookie_t *done,
|
||||
dma_cookie_t *used)
|
||||
{
|
||||
struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
|
||||
dma_cookie_t last_used;
|
||||
dma_cookie_t last_complete;
|
||||
|
||||
sh_dmae_chan_ld_cleanup(sh_chan);
|
||||
|
||||
last_used = chan->cookie;
|
||||
last_complete = sh_chan->completed_cookie;
|
||||
if (last_complete == -EBUSY)
|
||||
last_complete = last_used;
|
||||
|
||||
if (done)
|
||||
*done = last_complete;
|
||||
|
||||
if (used)
|
||||
*used = last_used;
|
||||
|
||||
return dma_async_is_complete(cookie, last_complete, last_used);
|
||||
}
|
||||
|
||||
static irqreturn_t sh_dmae_interrupt(int irq, void *data)
|
||||
{
|
||||
irqreturn_t ret = IRQ_NONE;
|
||||
struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
|
||||
u32 chcr = sh_dmae_readl(sh_chan, CHCR);
|
||||
|
||||
if (chcr & CHCR_TE) {
|
||||
/* DMA stop */
|
||||
dmae_halt(sh_chan);
|
||||
|
||||
ret = IRQ_HANDLED;
|
||||
tasklet_schedule(&sh_chan->tasklet);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CPU_SH4)
|
||||
static irqreturn_t sh_dmae_err(int irq, void *data)
|
||||
{
|
||||
int err = 0;
|
||||
struct sh_dmae_device *shdev = (struct sh_dmae_device *)data;
|
||||
|
||||
/* IRQ Multi */
|
||||
if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
|
||||
int cnt = 0;
|
||||
switch (irq) {
|
||||
#if defined(DMTE6_IRQ) && defined(DMAE1_IRQ)
|
||||
case DMTE6_IRQ:
|
||||
cnt++;
|
||||
#endif
|
||||
case DMTE0_IRQ:
|
||||
if (dmaor_read_reg(cnt) & (DMAOR_NMIF | DMAOR_AE)) {
|
||||
disable_irq(irq);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
default:
|
||||
return IRQ_NONE;
|
||||
}
|
||||
} else {
|
||||
/* reset dma controller */
|
||||
err = sh_dmae_rst(0);
|
||||
if (err)
|
||||
return err;
|
||||
if (shdev->pdata.mode & SHDMA_DMAOR1) {
|
||||
err = sh_dmae_rst(1);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
disable_irq(irq);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static void dmae_do_tasklet(unsigned long data)
|
||||
{
|
||||
struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
|
||||
struct sh_desc *desc, *_desc, *cur_desc = NULL;
|
||||
u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
|
||||
list_for_each_entry_safe(desc, _desc,
|
||||
&sh_chan->ld_queue, node) {
|
||||
if ((desc->hw.sar + desc->hw.tcr) == sar_buf) {
|
||||
cur_desc = desc;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (cur_desc) {
|
||||
switch (cur_desc->async_tx.cookie) {
|
||||
case 0: /* other desc data */
|
||||
break;
|
||||
case -EBUSY: /* last desc */
|
||||
sh_chan->completed_cookie =
|
||||
cur_desc->async_tx.cookie;
|
||||
break;
|
||||
default: /* first desc ( 0 < )*/
|
||||
sh_chan->completed_cookie =
|
||||
cur_desc->async_tx.cookie - 1;
|
||||
break;
|
||||
}
|
||||
cur_desc->mark = DESC_COMP;
|
||||
}
|
||||
/* Next desc */
|
||||
sh_chan_xfer_ld_queue(sh_chan);
|
||||
sh_dmae_chan_ld_cleanup(sh_chan);
|
||||
}
|
||||
|
||||
static unsigned int get_dmae_irq(unsigned int id)
|
||||
{
|
||||
unsigned int irq = 0;
|
||||
if (id < ARRAY_SIZE(dmte_irq_map))
|
||||
irq = dmte_irq_map[id];
|
||||
return irq;
|
||||
}
|
||||
|
||||
static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id)
|
||||
{
|
||||
int err;
|
||||
unsigned int irq = get_dmae_irq(id);
|
||||
unsigned long irqflags = IRQF_DISABLED;
|
||||
struct sh_dmae_chan *new_sh_chan;
|
||||
|
||||
/* alloc channel */
|
||||
new_sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL);
|
||||
if (!new_sh_chan) {
|
||||
dev_err(shdev->common.dev, "No free memory for allocating "
|
||||
"dma channels!\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
new_sh_chan->dev = shdev->common.dev;
|
||||
new_sh_chan->id = id;
|
||||
|
||||
/* Init DMA tasklet */
|
||||
tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet,
|
||||
(unsigned long)new_sh_chan);
|
||||
|
||||
/* Init the channel */
|
||||
dmae_init(new_sh_chan);
|
||||
|
||||
spin_lock_init(&new_sh_chan->desc_lock);
|
||||
|
||||
/* Init descripter manage list */
|
||||
INIT_LIST_HEAD(&new_sh_chan->ld_queue);
|
||||
INIT_LIST_HEAD(&new_sh_chan->ld_free);
|
||||
|
||||
/* copy struct dma_device */
|
||||
new_sh_chan->common.device = &shdev->common;
|
||||
|
||||
/* Add the channel to DMA device channel list */
|
||||
list_add_tail(&new_sh_chan->common.device_node,
|
||||
&shdev->common.channels);
|
||||
shdev->common.chancnt++;
|
||||
|
||||
if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
|
||||
irqflags = IRQF_SHARED;
|
||||
#if defined(DMTE6_IRQ)
|
||||
if (irq >= DMTE6_IRQ)
|
||||
irq = DMTE6_IRQ;
|
||||
else
|
||||
#endif
|
||||
irq = DMTE0_IRQ;
|
||||
}
|
||||
|
||||
snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
|
||||
"sh-dmae%d", new_sh_chan->id);
|
||||
|
||||
/* set up channel irq */
|
||||
err = request_irq(irq, &sh_dmae_interrupt,
|
||||
irqflags, new_sh_chan->dev_id, new_sh_chan);
|
||||
if (err) {
|
||||
dev_err(shdev->common.dev, "DMA channel %d request_irq error "
|
||||
"with return %d\n", id, err);
|
||||
goto err_no_irq;
|
||||
}
|
||||
|
||||
/* CHCR register control function */
|
||||
new_sh_chan->set_chcr = dmae_set_chcr;
|
||||
/* DMARS register control function */
|
||||
new_sh_chan->set_dmars = dmae_set_dmars;
|
||||
|
||||
shdev->chan[id] = new_sh_chan;
|
||||
return 0;
|
||||
|
||||
err_no_irq:
|
||||
/* remove from dmaengine device node */
|
||||
list_del(&new_sh_chan->common.device_node);
|
||||
kfree(new_sh_chan);
|
||||
return err;
|
||||
}
|
||||
|
||||
static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) {
|
||||
if (shdev->chan[i]) {
|
||||
struct sh_dmae_chan *shchan = shdev->chan[i];
|
||||
if (!(shdev->pdata.mode & SHDMA_MIX_IRQ))
|
||||
free_irq(dmte_irq_map[i], shchan);
|
||||
|
||||
list_del(&shchan->common.device_node);
|
||||
kfree(shchan);
|
||||
shdev->chan[i] = NULL;
|
||||
}
|
||||
}
|
||||
shdev->common.chancnt = 0;
|
||||
}
|
||||
|
||||
static int __init sh_dmae_probe(struct platform_device *pdev)
|
||||
{
|
||||
int err = 0, cnt, ecnt;
|
||||
unsigned long irqflags = IRQF_DISABLED;
|
||||
#if defined(CONFIG_CPU_SH4)
|
||||
int eirq[] = { DMAE0_IRQ,
|
||||
#if defined(DMAE1_IRQ)
|
||||
DMAE1_IRQ
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
struct sh_dmae_device *shdev;
|
||||
|
||||
shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL);
|
||||
if (!shdev) {
|
||||
dev_err(&pdev->dev, "No enough memory\n");
|
||||
err = -ENOMEM;
|
||||
goto shdev_err;
|
||||
}
|
||||
|
||||
/* get platform data */
|
||||
if (!pdev->dev.platform_data)
|
||||
goto shdev_err;
|
||||
|
||||
/* platform data */
|
||||
memcpy(&shdev->pdata, pdev->dev.platform_data,
|
||||
sizeof(struct sh_dmae_pdata));
|
||||
|
||||
/* reset dma controller */
|
||||
err = sh_dmae_rst(0);
|
||||
if (err)
|
||||
goto rst_err;
|
||||
|
||||
/* SH7780/85/23 has DMAOR1 */
|
||||
if (shdev->pdata.mode & SHDMA_DMAOR1) {
|
||||
err = sh_dmae_rst(1);
|
||||
if (err)
|
||||
goto rst_err;
|
||||
}
|
||||
|
||||
INIT_LIST_HEAD(&shdev->common.channels);
|
||||
|
||||
dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask);
|
||||
shdev->common.device_alloc_chan_resources
|
||||
= sh_dmae_alloc_chan_resources;
|
||||
shdev->common.device_free_chan_resources = sh_dmae_free_chan_resources;
|
||||
shdev->common.device_prep_dma_memcpy = sh_dmae_prep_memcpy;
|
||||
shdev->common.device_is_tx_complete = sh_dmae_is_complete;
|
||||
shdev->common.device_issue_pending = sh_dmae_memcpy_issue_pending;
|
||||
shdev->common.dev = &pdev->dev;
|
||||
|
||||
#if defined(CONFIG_CPU_SH4)
|
||||
/* Non Mix IRQ mode SH7722/SH7730 etc... */
|
||||
if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
|
||||
irqflags = IRQF_SHARED;
|
||||
eirq[0] = DMTE0_IRQ;
|
||||
#if defined(DMTE6_IRQ) && defined(DMAE1_IRQ)
|
||||
eirq[1] = DMTE6_IRQ;
|
||||
#endif
|
||||
}
|
||||
|
||||
for (ecnt = 0 ; ecnt < ARRAY_SIZE(eirq); ecnt++) {
|
||||
err = request_irq(eirq[ecnt], sh_dmae_err,
|
||||
irqflags, "DMAC Address Error", shdev);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "DMA device request_irq"
|
||||
"error (irq %d) with return %d\n",
|
||||
eirq[ecnt], err);
|
||||
goto eirq_err;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_CPU_SH4 */
|
||||
|
||||
/* Create DMA Channel */
|
||||
for (cnt = 0 ; cnt < MAX_DMA_CHANNELS ; cnt++) {
|
||||
err = sh_dmae_chan_probe(shdev, cnt);
|
||||
if (err)
|
||||
goto chan_probe_err;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, shdev);
|
||||
dma_async_device_register(&shdev->common);
|
||||
|
||||
return err;
|
||||
|
||||
chan_probe_err:
|
||||
sh_dmae_chan_remove(shdev);
|
||||
|
||||
eirq_err:
|
||||
for (ecnt-- ; ecnt >= 0; ecnt--)
|
||||
free_irq(eirq[ecnt], shdev);
|
||||
|
||||
rst_err:
|
||||
kfree(shdev);
|
||||
|
||||
shdev_err:
|
||||
return err;
|
||||
}
|
||||
|
||||
static int __exit sh_dmae_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
|
||||
|
||||
dma_async_device_unregister(&shdev->common);
|
||||
|
||||
if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
|
||||
free_irq(DMTE0_IRQ, shdev);
|
||||
#if defined(DMTE6_IRQ)
|
||||
free_irq(DMTE6_IRQ, shdev);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* channel data remove */
|
||||
sh_dmae_chan_remove(shdev);
|
||||
|
||||
if (!(shdev->pdata.mode & SHDMA_MIX_IRQ)) {
|
||||
free_irq(DMAE0_IRQ, shdev);
|
||||
#if defined(DMAE1_IRQ)
|
||||
free_irq(DMAE1_IRQ, shdev);
|
||||
#endif
|
||||
}
|
||||
kfree(shdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sh_dmae_shutdown(struct platform_device *pdev)
|
||||
{
|
||||
struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
|
||||
sh_dmae_ctl_stop(0);
|
||||
if (shdev->pdata.mode & SHDMA_DMAOR1)
|
||||
sh_dmae_ctl_stop(1);
|
||||
}
|
||||
|
||||
static struct platform_driver sh_dmae_driver = {
|
||||
.remove = __exit_p(sh_dmae_remove),
|
||||
.shutdown = sh_dmae_shutdown,
|
||||
.driver = {
|
||||
.name = "sh-dma-engine",
|
||||
},
|
||||
};
|
||||
|
||||
static int __init sh_dmae_init(void)
|
||||
{
|
||||
return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
|
||||
}
|
||||
module_init(sh_dmae_init);
|
||||
|
||||
static void __exit sh_dmae_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&sh_dmae_driver);
|
||||
}
|
||||
module_exit(sh_dmae_exit);
|
||||
|
||||
MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
|
||||
MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
64
drivers/dma/shdma.h
Normal file
64
drivers/dma/shdma.h
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
/*
|
||||
* Renesas SuperH DMA Engine support
|
||||
*
|
||||
* Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
|
||||
* Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
#ifndef __DMA_SHDMA_H
|
||||
#define __DMA_SHDMA_H
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/dmapool.h>
|
||||
#include <linux/dmaengine.h>
|
||||
|
||||
#define SH_DMA_TCR_MAX 0x00FFFFFF /* 16MB */
|
||||
|
||||
struct sh_dmae_regs {
|
||||
u32 sar; /* SAR / source address */
|
||||
u32 dar; /* DAR / destination address */
|
||||
u32 tcr; /* TCR / transfer count */
|
||||
};
|
||||
|
||||
struct sh_desc {
|
||||
struct list_head tx_list;
|
||||
struct sh_dmae_regs hw;
|
||||
struct list_head node;
|
||||
struct dma_async_tx_descriptor async_tx;
|
||||
int mark;
|
||||
};
|
||||
|
||||
struct sh_dmae_chan {
|
||||
dma_cookie_t completed_cookie; /* The maximum cookie completed */
|
||||
spinlock_t desc_lock; /* Descriptor operation lock */
|
||||
struct list_head ld_queue; /* Link descriptors queue */
|
||||
struct list_head ld_free; /* Link descriptors free */
|
||||
struct dma_chan common; /* DMA common channel */
|
||||
struct device *dev; /* Channel device */
|
||||
struct tasklet_struct tasklet; /* Tasklet */
|
||||
int descs_allocated; /* desc count */
|
||||
int id; /* Raw id of this channel */
|
||||
char dev_id[16]; /* unique name per DMAC of channel */
|
||||
|
||||
/* Set chcr */
|
||||
int (*set_chcr)(struct sh_dmae_chan *sh_chan, u32 regs);
|
||||
/* Set DMA resource */
|
||||
int (*set_dmars)(struct sh_dmae_chan *sh_chan, u16 res);
|
||||
};
|
||||
|
||||
struct sh_dmae_device {
|
||||
struct dma_device common;
|
||||
struct sh_dmae_chan *chan[MAX_DMA_CHANNELS];
|
||||
struct sh_dmae_pdata pdata;
|
||||
};
|
||||
|
||||
#define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, common)
|
||||
#define to_sh_desc(lh) container_of(lh, struct sh_desc, node)
|
||||
#define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx)
|
||||
|
||||
#endif /* __DMA_SHDMA_H */
|
||||
Loading…
Reference in New Issue
Block a user