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[ARM] Feroceon: support old cores with ARM926 ID

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This enables the usage of some old Feroceon cores
for which the CPU ID is equal to the ARM926 ID.
Relevant for Feroceon-1850 and old Feroceon-2850.

Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Tzachi Perelstein 2007-11-06 10:35:40 +02:00 committed by Russell King
parent 3ebb5a2b44
commit d910a0aa21
2 changed files with 36 additions and 0 deletions
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9
arch/arm/mm/Kconfig
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@ -354,6 +354,15 @@ config CPU_FEROCEON
select CPU_COPY_V4WB if MMU
select CPU_TLB_V4WBI if MMU
config CPU_FEROCEON_OLD_ID
bool "Accept early Feroceon cores with an ARM926 ID"
depends on CPU_FEROCEON && !CPU_ARM926T
default y
help
This enables the usage of some old Feroceon cores
for which the CPU ID is equal to the ARM926 ID.
Relevant for Feroceon-1850 and early Feroceon-2850.
# ARMv6
config CPU_V6
bool "Support ARM V6 processor"

27
arch/arm/mm/proc-feroceon.S
View File

@ -453,6 +453,33 @@ cpu_feroceon_name:
.section ".proc.info.init", #alloc, #execinstr
#ifdef CONFIG_CPU_FEROCEON_OLD_ID
.type __feroceon_old_id_proc_info,#object
__feroceon_old_id_proc_info:
.long 0x41069260
.long 0xfffffff0
.long PMD_TYPE_SECT | \
PMD_SECT_BUFFERABLE | \
PMD_SECT_CACHEABLE | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __feroceon_setup
.long cpu_arch_name
.long cpu_elf_name
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
.long cpu_feroceon_name
.long feroceon_processor_functions
.long v4wbi_tlb_fns
.long v4wb_user_fns
.long feroceon_cache_fns
.size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
#endif
.type __feroceon_proc_info,#object
__feroceon_proc_info:
.long 0x56055310