forked from luck/tmp_suning_uos_patched
Merge branch 'pci/host-imx6' into next
* pci/host-imx6: PCI: imx6: Add support for i.MX6 PCIe controller ARM: imx6q: Add PCIe bits to GPR syscon definition
This commit is contained in:
Bjorn Helgaas
commit
d95d3d53c7
@ -3,7 +3,7 @@
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Required properties:
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- compatible: should contain "snps,dw-pcie" to identify the
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core, plus an identifier for the specific instance, such
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as "samsung,exynos5440-pcie".
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as "samsung,exynos5440-pcie" or "fsl,imx6q-pcie".
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- reg: base addresses and lengths of the pcie controller,
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the phy controller, additional register for the phy controller.
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- interrupts: interrupt values for level interrupt,
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@ -21,6 +21,11 @@ Required properties:
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- num-lanes: number of lanes to use
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- reset-gpio: gpio pin number of power good signal
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Optional properties for fsl,imx6q-pcie
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- power-on-gpio: gpio pin number of power-enable signal
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- wake-up-gpio: gpio pin number of incoming wakeup signal
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- disable-gpio: gpio pin number of outgoing rfkill/endpoint disable signal
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Example:
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SoC specific DT Entry:
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@ -15,6 +15,12 @@ config PCI_EXYNOS
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select PCIEPORTBUS
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select PCIE_DW
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config PCI_IMX6
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bool "Freescale i.MX6 PCIe controller"
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depends on SOC_IMX6Q
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select PCIEPORTBUS
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select PCIE_DW
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config PCI_TEGRA
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bool "NVIDIA Tegra PCIe controller"
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depends on ARCH_TEGRA
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@ -1,4 +1,5 @@
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obj-$(CONFIG_PCIE_DW) += pcie-designware.o
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obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
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obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
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obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
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obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
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575
drivers/pci/host/pci-imx6.c
Normal file
575
drivers/pci/host/pci-imx6.c
Normal file
@ -0,0 +1,575 @@
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/*
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* PCIe host controller driver for Freescale i.MX6 SoCs
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*
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* Copyright (C) 2013 Kosagi
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* http://www.kosagi.com
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*
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* Author: Sean Cross <xobs@kosagi.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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#include <linux/module.h>
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#include <linux/of_gpio.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/resource.h>
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#include <linux/signal.h>
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#include <linux/types.h>
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#include "pcie-designware.h"
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#define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
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struct imx6_pcie {
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int reset_gpio;
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int power_on_gpio;
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int wake_up_gpio;
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int disable_gpio;
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struct clk *lvds_gate;
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struct clk *sata_ref_100m;
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struct clk *pcie_ref_125m;
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struct clk *pcie_axi;
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struct pcie_port pp;
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struct regmap *iomuxc_gpr;
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void __iomem *mem_base;
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};
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/* PCIe Port Logic registers (memory-mapped) */
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#define PL_OFFSET 0x700
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#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
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#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
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#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
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#define PCIE_PHY_CTRL_DATA_LOC 0
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#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
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#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
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#define PCIE_PHY_CTRL_WR_LOC 18
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#define PCIE_PHY_CTRL_RD_LOC 19
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#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
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#define PCIE_PHY_STAT_ACK_LOC 16
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/* PHY registers (not memory-mapped) */
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#define PCIE_PHY_RX_ASIC_OUT 0x100D
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#define PHY_RX_OVRD_IN_LO 0x1005
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#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
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#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
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static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
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{
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u32 val;
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u32 max_iterations = 10;
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u32 wait_counter = 0;
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do {
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val = readl(dbi_base + PCIE_PHY_STAT);
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val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
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wait_counter++;
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if (val == exp_val)
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return 0;
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udelay(1);
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} while (wait_counter < max_iterations);
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return -ETIMEDOUT;
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}
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static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
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{
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u32 val;
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int ret;
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val = addr << PCIE_PHY_CTRL_DATA_LOC;
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writel(val, dbi_base + PCIE_PHY_CTRL);
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val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
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writel(val, dbi_base + PCIE_PHY_CTRL);
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ret = pcie_phy_poll_ack(dbi_base, 1);
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if (ret)
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return ret;
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val = addr << PCIE_PHY_CTRL_DATA_LOC;
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writel(val, dbi_base + PCIE_PHY_CTRL);
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ret = pcie_phy_poll_ack(dbi_base, 0);
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if (ret)
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return ret;
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return 0;
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}
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/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
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static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
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{
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u32 val, phy_ctl;
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int ret;
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ret = pcie_phy_wait_ack(dbi_base, addr);
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if (ret)
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return ret;
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/* assert Read signal */
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phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
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writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
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ret = pcie_phy_poll_ack(dbi_base, 1);
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if (ret)
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return ret;
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val = readl(dbi_base + PCIE_PHY_STAT);
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*data = val & 0xffff;
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/* deassert Read signal */
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writel(0x00, dbi_base + PCIE_PHY_CTRL);
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ret = pcie_phy_poll_ack(dbi_base, 0);
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if (ret)
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return ret;
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return 0;
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}
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static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
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{
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u32 var;
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int ret;
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/* write addr */
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/* cap addr */
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ret = pcie_phy_wait_ack(dbi_base, addr);
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if (ret)
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return ret;
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var = data << PCIE_PHY_CTRL_DATA_LOC;
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writel(var, dbi_base + PCIE_PHY_CTRL);
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/* capture data */
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var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
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writel(var, dbi_base + PCIE_PHY_CTRL);
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ret = pcie_phy_poll_ack(dbi_base, 1);
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if (ret)
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return ret;
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/* deassert cap data */
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var = data << PCIE_PHY_CTRL_DATA_LOC;
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writel(var, dbi_base + PCIE_PHY_CTRL);
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/* wait for ack de-assertion */
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ret = pcie_phy_poll_ack(dbi_base, 0);
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if (ret)
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return ret;
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/* assert wr signal */
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var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
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writel(var, dbi_base + PCIE_PHY_CTRL);
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/* wait for ack */
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ret = pcie_phy_poll_ack(dbi_base, 1);
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if (ret)
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return ret;
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/* deassert wr signal */
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var = data << PCIE_PHY_CTRL_DATA_LOC;
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writel(var, dbi_base + PCIE_PHY_CTRL);
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/* wait for ack de-assertion */
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ret = pcie_phy_poll_ack(dbi_base, 0);
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if (ret)
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return ret;
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writel(0x0, dbi_base + PCIE_PHY_CTRL);
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return 0;
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}
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/* Added for PCI abort handling */
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static int imx6q_pcie_abort_handler(unsigned long addr,
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unsigned int fsr, struct pt_regs *regs)
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{
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/*
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* If it was an imprecise abort, then we need to correct the
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* return address to be _after_ the instruction.
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*/
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if (fsr & (1 << 10))
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regs->ARM_pc += 4;
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return 0;
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}
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static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
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{
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struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
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gpio_set_value(imx6_pcie->reset_gpio, 0);
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msleep(100);
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gpio_set_value(imx6_pcie->reset_gpio, 1);
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return 0;
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}
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static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
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{
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struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
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int ret;
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if (gpio_is_valid(imx6_pcie->power_on_gpio))
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gpio_set_value(imx6_pcie->power_on_gpio, 1);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
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ret = clk_prepare_enable(imx6_pcie->sata_ref_100m);
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if (ret) {
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dev_err(pp->dev, "unable to enable sata_ref_100m\n");
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goto err_sata_ref;
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}
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ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m);
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if (ret) {
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dev_err(pp->dev, "unable to enable pcie_ref_125m\n");
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goto err_pcie_ref;
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}
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ret = clk_prepare_enable(imx6_pcie->lvds_gate);
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if (ret) {
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dev_err(pp->dev, "unable to enable lvds_gate\n");
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goto err_lvds_gate;
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}
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ret = clk_prepare_enable(imx6_pcie->pcie_axi);
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if (ret) {
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dev_err(pp->dev, "unable to enable pcie_axi\n");
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goto err_pcie_axi;
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}
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/* allow the clocks to stabilize */
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usleep_range(200, 500);
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return 0;
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err_pcie_axi:
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clk_disable_unprepare(imx6_pcie->lvds_gate);
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err_lvds_gate:
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clk_disable_unprepare(imx6_pcie->pcie_ref_125m);
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err_pcie_ref:
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clk_disable_unprepare(imx6_pcie->sata_ref_100m);
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err_sata_ref:
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return ret;
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||||
}
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static void imx6_pcie_init_phy(struct pcie_port *pp)
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{
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struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
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||||
|
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
|
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IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
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|
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/* configure constant input signal to the pcie ctrl and phy */
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||||
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
|
||||
IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
|
||||
IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
|
||||
|
||||
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
|
||||
IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
|
||||
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
|
||||
IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
|
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
|
||||
IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
|
||||
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
|
||||
IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
|
||||
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
|
||||
IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
|
||||
}
|
||||
|
||||
static void imx6_pcie_host_init(struct pcie_port *pp)
|
||||
{
|
||||
int count = 0;
|
||||
struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
|
||||
|
||||
imx6_pcie_assert_core_reset(pp);
|
||||
|
||||
imx6_pcie_init_phy(pp);
|
||||
|
||||
imx6_pcie_deassert_core_reset(pp);
|
||||
|
||||
dw_pcie_setup_rc(pp);
|
||||
|
||||
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
|
||||
IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
|
||||
|
||||
while (!dw_pcie_link_up(pp)) {
|
||||
usleep_range(100, 1000);
|
||||
count++;
|
||||
if (count >= 10) {
|
||||
dev_err(pp->dev, "phy link never came up\n");
|
||||
dev_dbg(pp->dev,
|
||||
"DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
|
||||
readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
|
||||
readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static int imx6_pcie_link_up(struct pcie_port *pp)
|
||||
{
|
||||
u32 rc, ltssm, rx_valid, temp;
|
||||
|
||||
/* link is debug bit 36, debug register 1 starts at bit 32 */
|
||||
rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32));
|
||||
if (rc)
|
||||
return -EAGAIN;
|
||||
|
||||
/*
|
||||
* From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
|
||||
* Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
|
||||
* If (MAC/LTSSM.state == Recovery.RcvrLock)
|
||||
* && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
|
||||
* to gen2 is stuck
|
||||
*/
|
||||
pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
|
||||
ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
|
||||
|
||||
if (rx_valid & 0x01)
|
||||
return 0;
|
||||
|
||||
if (ltssm != 0x0d)
|
||||
return 0;
|
||||
|
||||
dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
|
||||
|
||||
pcie_phy_read(pp->dbi_base,
|
||||
PHY_RX_OVRD_IN_LO, &temp);
|
||||
temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN
|
||||
| PHY_RX_OVRD_IN_LO_RX_PLL_EN);
|
||||
pcie_phy_write(pp->dbi_base,
|
||||
PHY_RX_OVRD_IN_LO, temp);
|
||||
|
||||
usleep_range(2000, 3000);
|
||||
|
||||
pcie_phy_read(pp->dbi_base,
|
||||
PHY_RX_OVRD_IN_LO, &temp);
|
||||
temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN
|
||||
| PHY_RX_OVRD_IN_LO_RX_PLL_EN);
|
||||
pcie_phy_write(pp->dbi_base,
|
||||
PHY_RX_OVRD_IN_LO, temp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct pcie_host_ops imx6_pcie_host_ops = {
|
||||
.link_up = imx6_pcie_link_up,
|
||||
.host_init = imx6_pcie_host_init,
|
||||
};
|
||||
|
||||
static int imx6_add_pcie_port(struct pcie_port *pp,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
pp->irq = platform_get_irq(pdev, 0);
|
||||
if (!pp->irq) {
|
||||
dev_err(&pdev->dev, "failed to get irq\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
pp->root_bus_nr = -1;
|
||||
pp->ops = &imx6_pcie_host_ops;
|
||||
|
||||
spin_lock_init(&pp->conf_lock);
|
||||
ret = dw_pcie_host_init(pp);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to initialize host\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init imx6_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct imx6_pcie *imx6_pcie;
|
||||
struct pcie_port *pp;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct resource *dbi_base;
|
||||
int ret;
|
||||
|
||||
imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
|
||||
if (!imx6_pcie)
|
||||
return -ENOMEM;
|
||||
|
||||
pp = &imx6_pcie->pp;
|
||||
pp->dev = &pdev->dev;
|
||||
|
||||
/* Added for PCI abort handling */
|
||||
hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
|
||||
"imprecise external abort");
|
||||
|
||||
dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!dbi_base) {
|
||||
dev_err(&pdev->dev, "dbi_base memory resource not found\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
|
||||
if (IS_ERR(pp->dbi_base)) {
|
||||
dev_err(&pdev->dev, "unable to remap dbi_base\n");
|
||||
ret = PTR_ERR(pp->dbi_base);
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* Fetch GPIOs */
|
||||
imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
|
||||
if (!gpio_is_valid(imx6_pcie->reset_gpio)) {
|
||||
dev_err(&pdev->dev, "no reset-gpio defined\n");
|
||||
ret = -ENODEV;
|
||||
}
|
||||
ret = devm_gpio_request_one(&pdev->dev,
|
||||
imx6_pcie->reset_gpio,
|
||||
GPIOF_OUT_INIT_LOW,
|
||||
"PCIe reset");
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "unable to get reset gpio\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0);
|
||||
if (gpio_is_valid(imx6_pcie->power_on_gpio)) {
|
||||
ret = devm_gpio_request_one(&pdev->dev,
|
||||
imx6_pcie->power_on_gpio,
|
||||
GPIOF_OUT_INIT_LOW,
|
||||
"PCIe power enable");
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "unable to get power-on gpio\n");
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0);
|
||||
if (gpio_is_valid(imx6_pcie->wake_up_gpio)) {
|
||||
ret = devm_gpio_request_one(&pdev->dev,
|
||||
imx6_pcie->wake_up_gpio,
|
||||
GPIOF_IN,
|
||||
"PCIe wake up");
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "unable to get wake-up gpio\n");
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0);
|
||||
if (gpio_is_valid(imx6_pcie->disable_gpio)) {
|
||||
ret = devm_gpio_request_one(&pdev->dev,
|
||||
imx6_pcie->disable_gpio,
|
||||
GPIOF_OUT_INIT_HIGH,
|
||||
"PCIe disable endpoint");
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "unable to get disable-ep gpio\n");
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
/* Fetch clocks */
|
||||
imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate");
|
||||
if (IS_ERR(imx6_pcie->lvds_gate)) {
|
||||
dev_err(&pdev->dev,
|
||||
"lvds_gate clock select missing or invalid\n");
|
||||
ret = PTR_ERR(imx6_pcie->lvds_gate);
|
||||
goto err;
|
||||
}
|
||||
|
||||
imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m");
|
||||
if (IS_ERR(imx6_pcie->sata_ref_100m)) {
|
||||
dev_err(&pdev->dev,
|
||||
"sata_ref_100m clock source missing or invalid\n");
|
||||
ret = PTR_ERR(imx6_pcie->sata_ref_100m);
|
||||
goto err;
|
||||
}
|
||||
|
||||
imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m");
|
||||
if (IS_ERR(imx6_pcie->pcie_ref_125m)) {
|
||||
dev_err(&pdev->dev,
|
||||
"pcie_ref_125m clock source missing or invalid\n");
|
||||
ret = PTR_ERR(imx6_pcie->pcie_ref_125m);
|
||||
goto err;
|
||||
}
|
||||
|
||||
imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi");
|
||||
if (IS_ERR(imx6_pcie->pcie_axi)) {
|
||||
dev_err(&pdev->dev,
|
||||
"pcie_axi clock source missing or invalid\n");
|
||||
ret = PTR_ERR(imx6_pcie->pcie_axi);
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* Grab GPR config register range */
|
||||
imx6_pcie->iomuxc_gpr =
|
||||
syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
|
||||
if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
|
||||
dev_err(&pdev->dev, "unable to find iomuxc registers\n");
|
||||
ret = PTR_ERR(imx6_pcie->iomuxc_gpr);
|
||||
goto err;
|
||||
}
|
||||
|
||||
ret = imx6_add_pcie_port(pp, pdev);
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
|
||||
platform_set_drvdata(pdev, imx6_pcie);
|
||||
return 0;
|
||||
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id imx6_pcie_of_match[] = {
|
||||
{ .compatible = "fsl,imx6q-pcie", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
|
||||
|
||||
static struct platform_driver imx6_pcie_driver = {
|
||||
.driver = {
|
||||
.name = "imx6q-pcie",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(imx6_pcie_of_match),
|
||||
},
|
||||
};
|
||||
|
||||
/* Freescale PCIe driver does not allow module unload */
|
||||
|
||||
static int __init imx6_pcie_init(void)
|
||||
{
|
||||
return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
|
||||
}
|
||||
module_init(imx6_pcie_init);
|
||||
|
||||
MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
|
||||
MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@ -241,6 +241,12 @@
|
||||
|
||||
#define IMX6Q_GPR5_L2_CLK_STOP BIT(8)
|
||||
|
||||
#define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25)
|
||||
#define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18)
|
||||
#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12)
|
||||
#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB (0x3f << 6)
|
||||
#define IMX6Q_GPR8_TX_DEEMPH_GEN1 (0x3f << 0)
|
||||
|
||||
#define IMX6Q_GPR9_TZASC2_BYP BIT(1)
|
||||
#define IMX6Q_GPR9_TZASC1_BYP BIT(0)
|
||||
|
||||
@ -273,7 +279,9 @@
|
||||
#define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26)
|
||||
#define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25)
|
||||
#define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24)
|
||||
#define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12)
|
||||
#define IMX6Q_GPR12_PCIE_CTL_2 BIT(10)
|
||||
#define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4)
|
||||
|
||||
#define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30)
|
||||
#define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user