forked from luck/tmp_suning_uos_patched
iwlwifi: move txq_ctx_stop into iwl-tx.c
This patch moves txq_ctx_stop into iwl-tx.c iwlcore module. Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
parent
46315e0122
commit
da1bc4539f
@ -468,25 +468,13 @@ int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
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return ret;
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}
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static int iwl4965_disable_tx_fifo(struct iwl_priv *priv)
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/*
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* Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
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* must be called under priv->lock and mac access
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*/
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static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
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{
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&priv->lock, flags);
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ret = iwl_grab_nic_access(priv);
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if (unlikely(ret)) {
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IWL_ERROR("Tx fifo reset failed");
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spin_unlock_irqrestore(&priv->lock, flags);
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return ret;
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}
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iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
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iwl_release_nic_access(priv);
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
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}
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static int iwl4965_apm_init(struct iwl_priv *priv)
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@ -579,36 +567,6 @@ static void iwl4965_nic_config(struct iwl_priv *priv)
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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/**
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* iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
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*/
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void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
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{
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int txq_id;
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unsigned long flags;
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/* Stop each Tx DMA channel, and wait for it to be idle */
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for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
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spin_lock_irqsave(&priv->lock, flags);
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if (iwl_grab_nic_access(priv)) {
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spin_unlock_irqrestore(&priv->lock, flags);
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continue;
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}
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iwl_write_direct32(priv,
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FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
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iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
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FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
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(txq_id), 200);
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iwl_release_nic_access(priv);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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/* Deallocate memory for all Tx queues */
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iwl_hw_txq_ctx_free(priv);
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}
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static int iwl4965_apm_stop_master(struct iwl_priv *priv)
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{
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int ret = 0;
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@ -995,8 +953,7 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
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(1 << priv->hw_params.max_txq_num) - 1);
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/* Activate all Tx DMA/FIFO channels */
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iwl_write_prph(priv, IWL49_SCD_TXFACT,
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SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
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priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
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iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
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@ -3622,7 +3579,7 @@ static struct iwl_lib_ops iwl4965_lib = {
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.free_shared_mem = iwl4965_free_shared_mem,
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.shared_mem_rx_idx = iwl4965_shared_mem_rx_idx,
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.txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
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.disable_tx_fifo = iwl4965_disable_tx_fifo,
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.txq_set_sched = iwl4965_txq_set_sched,
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.rx_handler_setup = iwl4965_rx_handler_setup,
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.is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
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.alive_notify = iwl4965_alive_notify,
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@ -662,10 +662,10 @@ static int iwl5000_alive_notify(struct iwl_priv *priv)
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}
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iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
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(1 << priv->hw_params.max_txq_num) - 1);
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IWL_MASK(0, priv->hw_params.max_txq_num));
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iwl_write_prph(priv, IWL50_SCD_TXFACT,
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SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
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/* Activate all Tx DMA/FIFO channels */
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priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
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iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
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/* map qos queues to fifos one-to-one */
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@ -839,25 +839,13 @@ static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
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}
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static int iwl5000_disable_tx_fifo(struct iwl_priv *priv)
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/*
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* Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
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* must be called under priv->lock and mac access
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*/
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static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
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{
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&priv->lock, flags);
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ret = iwl_grab_nic_access(priv);
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if (unlikely(ret)) {
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IWL_ERROR("Tx fifo reset failed");
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spin_unlock_irqrestore(&priv->lock, flags);
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return ret;
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}
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iwl_write_prph(priv, IWL50_SCD_TXFACT, 0);
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iwl_release_nic_access(priv);
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
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}
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/* Currently 5000 is the supperset of everything */
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@ -894,7 +882,7 @@ static struct iwl_lib_ops iwl5000_lib = {
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.free_shared_mem = iwl5000_free_shared_mem,
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.shared_mem_rx_idx = iwl5000_shared_mem_rx_idx,
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.txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
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.disable_tx_fifo = iwl5000_disable_tx_fifo,
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.txq_set_sched = iwl5000_txq_set_sched,
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.rx_handler_setup = iwl5000_rx_handler_setup,
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.is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
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.load_ucode = iwl5000_load_ucode,
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@ -110,7 +110,7 @@ struct iwl_lib_ops {
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/* setup Rx handler */
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void (*rx_handler_setup)(struct iwl_priv *priv);
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/* nic Tx fifo handling */
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int (*disable_tx_fifo)(struct iwl_priv *priv);
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void (*txq_set_sched)(struct iwl_priv *priv, u32 mask);
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/* alive notification after init uCode load */
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void (*init_alive_start)(struct iwl_priv *priv);
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/* alive notification */
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@ -686,7 +686,7 @@ extern void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv);
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extern void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv);
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extern int iwl4965_hw_rxq_stop(struct iwl_priv *priv);
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extern int iwl4965_hw_set_hw_params(struct iwl_priv *priv);
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extern void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv);
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extern void iwl_txq_ctx_stop(struct iwl_priv *priv);
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extern int iwl4965_hw_get_temperature(struct iwl_priv *priv);
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extern unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
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struct iwl_frame *frame, u8 rate);
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@ -136,6 +136,8 @@ static inline void iwl_set_bits16(__le16 *dst, u8 pos, u8 len, int val)
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#define KELVIN_TO_CELSIUS(x) ((x)-273)
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#define CELSIUS_TO_KELVIN(x) ((x)+273)
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#define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
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#define IEEE80211_CHAN_W_RADAR_DETECT 0x00000010
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@ -358,11 +358,6 @@
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* 7- 0: Enable (1), disable (0), one bit for each channel 0-7
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*/
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#define IWL49_SCD_TXFACT (IWL49_SCD_START_OFFSET + 0x1c)
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/* Mask to enable contiguous Tx DMA/FIFO channels between "lo" and "hi". */
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#define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \
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((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
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/*
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* Queue (x) Write Pointers (indexes, really!), one for each Tx queue.
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* Initialized and updated by driver as new TFDs are added to queue.
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@ -262,24 +262,6 @@ int iwl_queue_space(const struct iwl_queue *q)
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EXPORT_SYMBOL(iwl_queue_space);
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/**
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* iwl_hw_txq_ctx_free - Free TXQ Context
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*
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* Destroy all TX DMA queues and structures
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*/
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void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
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{
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int txq_id;
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/* Tx queues */
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for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
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iwl_tx_queue_free(priv, &priv->txq[txq_id]);
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/* Keep-warm buffer */
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iwl_kw_free(priv);
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}
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EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
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/**
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* iwl_queue_init - Initialize queue's high/low-water and read/write indexes
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*/
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@ -437,6 +419,24 @@ static int iwl_tx_queue_init(struct iwl_priv *priv,
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return 0;
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}
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/**
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* iwl_hw_txq_ctx_free - Free TXQ Context
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*
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* Destroy all TX DMA queues and structures
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*/
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void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
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{
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int txq_id;
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/* Tx queues */
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for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
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iwl_tx_queue_free(priv, &priv->txq[txq_id]);
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/* Keep-warm buffer */
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iwl_kw_free(priv);
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}
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EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
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/**
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* iwl_txq_ctx_reset - Reset TX queue context
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@ -449,6 +449,7 @@ int iwl_txq_ctx_reset(struct iwl_priv *priv)
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{
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int ret = 0;
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int txq_id, slots_num;
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unsigned long flags;
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iwl_kw_free(priv);
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@ -461,11 +462,19 @@ int iwl_txq_ctx_reset(struct iwl_priv *priv)
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IWL_ERROR("Keep Warm allocation failed");
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goto error_kw;
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}
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spin_lock_irqsave(&priv->lock, flags);
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ret = iwl_grab_nic_access(priv);
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if (unlikely(ret)) {
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spin_unlock_irqrestore(&priv->lock, flags);
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goto error_reset;
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}
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/* Turn off all Tx DMA fifos */
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ret = priv->cfg->ops->lib->disable_tx_fifo(priv);
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if (unlikely(ret))
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goto error_reset;
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priv->cfg->ops->lib->txq_set_sched(priv, 0);
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iwl_release_nic_access(priv);
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spin_unlock_irqrestore(&priv->lock, flags);
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/* Tell nic where to find the keep-warm buffer */
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ret = iwl_kw_init(priv);
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@ -474,8 +483,7 @@ int iwl_txq_ctx_reset(struct iwl_priv *priv)
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goto error_reset;
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}
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/* Alloc and init all (default 16) Tx queues,
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* including the command queue (#4) */
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/* Alloc and init all Tx queues, including the command queue (#4) */
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for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
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slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
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TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
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@ -496,6 +504,40 @@ int iwl_txq_ctx_reset(struct iwl_priv *priv)
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error_kw:
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return ret;
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}
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/**
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* iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
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*/
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void iwl_txq_ctx_stop(struct iwl_priv *priv)
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{
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int txq_id;
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unsigned long flags;
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/* Turn off all Tx DMA fifos */
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spin_lock_irqsave(&priv->lock, flags);
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if (iwl_grab_nic_access(priv)) {
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spin_unlock_irqrestore(&priv->lock, flags);
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return;
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}
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priv->cfg->ops->lib->txq_set_sched(priv, 0);
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/* Stop each Tx DMA channel, and wait for it to be idle */
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for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
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iwl_write_direct32(priv,
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FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
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iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
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FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
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(txq_id), 200);
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}
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iwl_release_nic_access(priv);
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spin_unlock_irqrestore(&priv->lock, flags);
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/* Deallocate memory for all Tx queues */
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iwl_hw_txq_ctx_free(priv);
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}
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EXPORT_SYMBOL(iwl_txq_ctx_stop);
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/*
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* handle build REPLY_TX command notification.
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@ -3404,7 +3404,7 @@ static void __iwl4965_down(struct iwl_priv *priv)
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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spin_unlock_irqrestore(&priv->lock, flags);
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iwl4965_hw_txq_ctx_stop(priv);
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iwl_txq_ctx_stop(priv);
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iwl4965_hw_rxq_stop(priv);
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spin_lock_irqsave(&priv->lock, flags);
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