forked from luck/tmp_suning_uos_patched
pinctrl: pinctrl-single: fix pcs_pin_dbg_show() when bits_per_mux is not zero
[ Upstream commit bd85125ea88513f637a62a72e8949c579c5c0a87 ]
A System Error (SError, followed by kernel panic) was detected when
trying to print the supported pins in a pinctrl device which supports
multiple pins per register. This change fixes the pcs_pin_dbg_show() in
pinctrl-single driver when bits_per_mux is not zero. In addition move
offset calculation and pin offset in register to common function.
Fixes: 4e7e8017a8
("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules")
Signed-off-by: Hanna Hawa <hhhawa@amazon.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Drew Fustini <drew@beagleboard.org>
Link: https://lore.kernel.org/r/20210319152133.28705-4-hhhawa@amazon.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
parent
353fcebf49
commit
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@ -270,20 +270,44 @@ static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
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writel(val, reg);
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}
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static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs,
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unsigned int pin)
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{
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unsigned int mux_bytes = pcs->width / BITS_PER_BYTE;
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if (pcs->bits_per_mux) {
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unsigned int pin_offset_bytes;
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pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
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return (pin_offset_bytes / mux_bytes) * mux_bytes;
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}
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return pin * mux_bytes;
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}
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static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs,
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unsigned int pin)
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{
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return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin;
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}
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static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
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struct seq_file *s,
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unsigned pin)
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{
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struct pcs_device *pcs;
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unsigned val, mux_bytes;
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unsigned int val;
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unsigned long offset;
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size_t pa;
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pcs = pinctrl_dev_get_drvdata(pctldev);
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mux_bytes = pcs->width / BITS_PER_BYTE;
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offset = pin * mux_bytes;
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offset = pcs_pin_reg_offset_get(pcs, pin);
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val = pcs->read(pcs->base + offset);
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if (pcs->bits_per_mux)
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val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin);
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pa = pcs->res->start + offset;
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seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
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@ -384,7 +408,6 @@ static int pcs_request_gpio(struct pinctrl_dev *pctldev,
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struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
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struct pcs_gpiofunc_range *frange = NULL;
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struct list_head *pos, *tmp;
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int mux_bytes = 0;
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unsigned data;
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/* If function mask is null, return directly. */
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@ -392,29 +415,27 @@ static int pcs_request_gpio(struct pinctrl_dev *pctldev,
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return -ENOTSUPP;
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list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
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u32 offset;
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frange = list_entry(pos, struct pcs_gpiofunc_range, node);
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if (pin >= frange->offset + frange->npins
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|| pin < frange->offset)
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continue;
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mux_bytes = pcs->width / BITS_PER_BYTE;
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offset = pcs_pin_reg_offset_get(pcs, pin);
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if (pcs->bits_per_mux) {
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int byte_num, offset, pin_shift;
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byte_num = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
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offset = (byte_num / mux_bytes) * mux_bytes;
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pin_shift = pin % (pcs->width / pcs->bits_per_pin) *
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pcs->bits_per_pin;
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int pin_shift = pcs_pin_shift_reg_get(pcs, pin);
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data = pcs->read(pcs->base + offset);
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data &= ~(pcs->fmask << pin_shift);
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data |= frange->gpiofunc << pin_shift;
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pcs->write(data, pcs->base + offset);
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} else {
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data = pcs->read(pcs->base + pin * mux_bytes);
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data = pcs->read(pcs->base + offset);
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data &= ~pcs->fmask;
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data |= frange->gpiofunc;
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pcs->write(data, pcs->base + pin * mux_bytes);
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pcs->write(data, pcs->base + offset);
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}
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break;
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}
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@ -726,14 +747,8 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs)
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for (i = 0; i < pcs->desc.npins; i++) {
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unsigned offset;
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int res;
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int byte_num;
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if (pcs->bits_per_mux) {
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byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
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offset = (byte_num / mux_bytes) * mux_bytes;
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} else {
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offset = i * mux_bytes;
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}
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offset = pcs_pin_reg_offset_get(pcs, i);
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res = pcs_add_pin(pcs, offset);
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if (res < 0) {
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dev_err(pcs->dev, "error adding pins: %i\n", res);
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