forked from luck/tmp_suning_uos_patched
can: ti_hecc: Convert TI HECC driver to DT only driver
This patch converts TI HECC driver to DT only driver. This results in removing ti_hecc.h containing now obsolete platform data. Former transceiver_switch callback function will be now modelled via regulator API. Signed-off-by: Anton Glukhov <anton.a.glukhov@gmail.com> Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
This commit is contained in:
Yegor Yefremov
Marc Kleine-Budde
parent
869a78a2be
commit
dabf54dd1c
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@ -17,25 +17,6 @@
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*
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*/
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/*
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* Your platform definitions should specify module ram offsets and interrupt
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* number to use as follows:
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*
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* static struct ti_hecc_platform_data am3517_evm_hecc_pdata = {
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* .scc_hecc_offset = 0,
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* .scc_ram_offset = 0x3000,
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* .hecc_ram_offset = 0x3000,
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* .mbx_offset = 0x2000,
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* .int_line = 0,
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* .revision = 1,
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* .transceiver_switch = hecc_phy_control,
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* };
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*
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* Please see include/linux/can/platform/ti_hecc.h for description of
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* above fields.
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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@ -46,11 +27,13 @@
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/can/dev.h>
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#include <linux/can/error.h>
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#include <linux/can/led.h>
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#include <linux/can/platform/ti_hecc.h>
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#define DRV_NAME "ti_hecc"
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#define HECC_MODULE_VERSION "0.7"
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@ -214,15 +197,14 @@ struct ti_hecc_priv {
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struct net_device *ndev;
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struct clk *clk;
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void __iomem *base;
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u32 scc_ram_offset;
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u32 hecc_ram_offset;
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u32 mbx_offset;
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u32 int_line;
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void __iomem *hecc_ram;
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void __iomem *mbx;
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bool use_hecc1int;
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spinlock_t mbx_lock; /* CANME register needs protection */
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u32 tx_head;
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u32 tx_tail;
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u32 rx_next;
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void (*transceiver_switch)(int);
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struct regulator *reg_xceiver;
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};
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static inline int get_tx_head_mb(struct ti_hecc_priv *priv)
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@ -242,20 +224,18 @@ static inline int get_tx_head_prio(struct ti_hecc_priv *priv)
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static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val)
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{
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__raw_writel(val, priv->base + priv->hecc_ram_offset + mbxno * 4);
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__raw_writel(val, priv->hecc_ram + mbxno * 4);
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}
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static inline void hecc_write_mbx(struct ti_hecc_priv *priv, u32 mbxno,
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u32 reg, u32 val)
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{
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__raw_writel(val, priv->base + priv->mbx_offset + mbxno * 0x10 +
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reg);
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__raw_writel(val, priv->mbx + mbxno * 0x10 + reg);
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}
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static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg)
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{
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return __raw_readl(priv->base + priv->mbx_offset + mbxno * 0x10 +
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reg);
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return __raw_readl(priv->mbx + mbxno * 0x10 + reg);
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}
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static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val)
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@ -311,11 +291,16 @@ static int ti_hecc_set_btc(struct ti_hecc_priv *priv)
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return 0;
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}
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static void ti_hecc_transceiver_switch(const struct ti_hecc_priv *priv,
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static int ti_hecc_transceiver_switch(const struct ti_hecc_priv *priv,
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int on)
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{
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if (priv->transceiver_switch)
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priv->transceiver_switch(on);
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if (!priv->reg_xceiver)
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return 0;
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if (on)
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return regulator_enable(priv->reg_xceiver);
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else
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return regulator_disable(priv->reg_xceiver);
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}
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static void ti_hecc_reset(struct net_device *ndev)
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@ -409,7 +394,7 @@ static void ti_hecc_start(struct net_device *ndev)
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/* Prevent message over-write & Enable interrupts */
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hecc_write(priv, HECC_CANOPC, HECC_SET_REG);
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if (priv->int_line) {
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if (priv->use_hecc1int) {
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hecc_write(priv, HECC_CANMIL, HECC_SET_REG);
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hecc_write(priv, HECC_CANGIM, HECC_CANGIM_DEF_MASK |
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HECC_CANGIM_I1EN | HECC_CANGIM_SIL);
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@ -760,7 +745,7 @@ static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id)
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unsigned long ack, flags;
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int_status = hecc_read(priv,
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(priv->int_line) ? HECC_CANGIF1 : HECC_CANGIF0);
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(priv->use_hecc1int) ? HECC_CANGIF1 : HECC_CANGIF0);
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if (!int_status)
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return IRQ_NONE;
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@ -806,7 +791,7 @@ static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id)
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}
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/* clear all interrupt conditions - read back to avoid spurious ints */
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if (priv->int_line) {
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if (priv->use_hecc1int) {
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hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);
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int_status = hecc_read(priv, HECC_CANGIF1);
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} else {
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@ -872,58 +857,87 @@ static const struct net_device_ops ti_hecc_netdev_ops = {
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.ndo_change_mtu = can_change_mtu,
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};
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static const struct of_device_id ti_hecc_dt_ids[] = {
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{
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.compatible = "ti,am3517-hecc",
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},
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{ }
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};
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MODULE_DEVICE_TABLE(of, ti_hecc_dt_ids);
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static int ti_hecc_probe(struct platform_device *pdev)
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{
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struct net_device *ndev = (struct net_device *)0;
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struct ti_hecc_priv *priv;
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struct ti_hecc_platform_data *pdata;
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struct resource *mem, *irq;
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void __iomem *addr;
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struct device_node *np = pdev->dev.of_node;
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struct resource *res, *irq;
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struct regulator *reg_xceiver;
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int err = -ENODEV;
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pdata = dev_get_platdata(&pdev->dev);
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if (!pdata) {
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dev_err(&pdev->dev, "No platform data\n");
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goto probe_exit;
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if (!IS_ENABLED(CONFIG_OF) || !np)
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return -EINVAL;
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reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
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if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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else if (IS_ERR(reg_xceiver))
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reg_xceiver = NULL;
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ndev = alloc_candev(sizeof(struct ti_hecc_priv), HECC_MAX_TX_MBOX);
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if (!ndev) {
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dev_err(&pdev->dev, "alloc_candev failed\n");
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return -ENOMEM;
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}
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priv = netdev_priv(ndev);
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/* handle hecc memory */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hecc");
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if (!res) {
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dev_err(&pdev->dev, "can't get IORESOURCE_MEM hecc\n");
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return -EINVAL;
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}
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!mem) {
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dev_err(&pdev->dev, "No mem resources\n");
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goto probe_exit;
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priv->base = devm_ioremap_resource(&pdev->dev, res);
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if (!priv->base) {
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dev_err(&pdev->dev, "hecc ioremap failed\n");
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return -ENOMEM;
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}
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/* handle hecc-ram memory */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hecc-ram");
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if (!res) {
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dev_err(&pdev->dev, "can't get IORESOURCE_MEM hecc-ram\n");
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return -EINVAL;
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}
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priv->hecc_ram = devm_ioremap_resource(&pdev->dev, res);
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if (!priv->hecc_ram) {
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dev_err(&pdev->dev, "hecc-ram ioremap failed\n");
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return -ENOMEM;
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}
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/* handle mbx memory */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mbx");
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if (!res) {
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dev_err(&pdev->dev, "can't get IORESOURCE_MEM mbx\n");
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return -EINVAL;
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}
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priv->mbx = devm_ioremap_resource(&pdev->dev, res);
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if (!priv->mbx) {
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dev_err(&pdev->dev, "mbx ioremap failed\n");
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return -ENOMEM;
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}
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irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (!irq) {
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dev_err(&pdev->dev, "No irq resource\n");
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goto probe_exit;
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}
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if (!request_mem_region(mem->start, resource_size(mem), pdev->name)) {
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dev_err(&pdev->dev, "HECC region already claimed\n");
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err = -EBUSY;
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goto probe_exit;
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}
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addr = ioremap(mem->start, resource_size(mem));
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if (!addr) {
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dev_err(&pdev->dev, "ioremap failed\n");
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err = -ENOMEM;
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goto probe_exit_free_region;
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}
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ndev = alloc_candev(sizeof(struct ti_hecc_priv), HECC_MAX_TX_MBOX);
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if (!ndev) {
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dev_err(&pdev->dev, "alloc_candev failed\n");
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err = -ENOMEM;
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goto probe_exit_iounmap;
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}
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priv = netdev_priv(ndev);
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priv->ndev = ndev;
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priv->base = addr;
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priv->scc_ram_offset = pdata->scc_ram_offset;
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priv->hecc_ram_offset = pdata->hecc_ram_offset;
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priv->mbx_offset = pdata->mbx_offset;
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priv->int_line = pdata->int_line;
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priv->transceiver_switch = pdata->transceiver_switch;
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priv->reg_xceiver = reg_xceiver;
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priv->use_hecc1int = of_property_read_bool(np, "ti,use-hecc1int");
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priv->can.bittiming_const = &ti_hecc_bittiming_const;
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priv->can.do_set_mode = ti_hecc_do_set_mode;
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@ -971,32 +985,23 @@ static int ti_hecc_probe(struct platform_device *pdev)
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clk_put(priv->clk);
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probe_exit_candev:
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free_candev(ndev);
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probe_exit_iounmap:
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iounmap(addr);
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probe_exit_free_region:
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release_mem_region(mem->start, resource_size(mem));
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probe_exit:
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return err;
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}
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static int ti_hecc_remove(struct platform_device *pdev)
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{
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struct resource *res;
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struct net_device *ndev = platform_get_drvdata(pdev);
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struct ti_hecc_priv *priv = netdev_priv(ndev);
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unregister_candev(ndev);
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clk_disable_unprepare(priv->clk);
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clk_put(priv->clk);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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iounmap(priv->base);
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release_mem_region(res->start, resource_size(res));
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free_candev(ndev);
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return 0;
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}
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#ifdef CONFIG_PM
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static int ti_hecc_suspend(struct platform_device *pdev, pm_message_t state)
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{
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@ -1045,6 +1050,7 @@ static int ti_hecc_resume(struct platform_device *pdev)
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static struct platform_driver ti_hecc_driver = {
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.driver = {
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.name = DRV_NAME,
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.of_match_table = ti_hecc_dt_ids,
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},
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.probe = ti_hecc_probe,
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.remove = ti_hecc_remove,
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@ -1,44 +0,0 @@
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#ifndef _CAN_PLATFORM_TI_HECC_H
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#define _CAN_PLATFORM_TI_HECC_H
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/*
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* TI HECC (High End CAN Controller) driver platform header
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*
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* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed as is WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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/**
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* struct hecc_platform_data - HECC Platform Data
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*
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* @scc_hecc_offset: mostly 0 - should really never change
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* @scc_ram_offset: SCC RAM offset
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* @hecc_ram_offset: HECC RAM offset
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* @mbx_offset: Mailbox RAM offset
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* @int_line: Interrupt line to use - 0 or 1
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* @version: version for future use
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* @transceiver_switch: platform specific callback fn for transceiver control
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*
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* Platform data structure to get all platform specific settings.
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* this structure also accounts the fact that the IP may have different
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* RAM and mailbox offsets for different SOC's
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*/
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struct ti_hecc_platform_data {
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u32 scc_hecc_offset;
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u32 scc_ram_offset;
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u32 hecc_ram_offset;
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u32 mbx_offset;
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u32 int_line;
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u32 version;
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void (*transceiver_switch) (int);
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};
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#endif /* !_CAN_PLATFORM_TI_HECC_H */
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