forked from luck/tmp_suning_uos_patched
MIPS: Alchemy: irq code and constant cleanup
replace au_readl/au_writel with __raw_readl/__raw_writel, and clean up IC-related stuff from the headers. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: Florian Fainelli <florian@openwrt.org> Cc: Wolfgang Grandegger <wg@grandegger.com> Patchwork: https://patchwork.linux-mips.org/patch/2354/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss
Ralf Baechle
parent
c1e58a3129
commit
dca7587185
@ -39,6 +39,36 @@
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#include <asm/mach-pb1x00/pb1000.h>
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#endif
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/* Interrupt Controller register offsets */
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#define IC_CFG0RD 0x40
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#define IC_CFG0SET 0x40
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#define IC_CFG0CLR 0x44
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#define IC_CFG1RD 0x48
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#define IC_CFG1SET 0x48
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#define IC_CFG1CLR 0x4C
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#define IC_CFG2RD 0x50
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#define IC_CFG2SET 0x50
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#define IC_CFG2CLR 0x54
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#define IC_REQ0INT 0x54
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#define IC_SRCRD 0x58
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#define IC_SRCSET 0x58
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#define IC_SRCCLR 0x5C
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#define IC_REQ1INT 0x5C
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#define IC_ASSIGNRD 0x60
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#define IC_ASSIGNSET 0x60
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#define IC_ASSIGNCLR 0x64
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#define IC_WAKERD 0x68
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#define IC_WAKESET 0x68
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#define IC_WAKECLR 0x6C
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#define IC_MASKRD 0x70
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#define IC_MASKSET 0x70
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#define IC_MASKCLR 0x74
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#define IC_RISINGRD 0x78
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#define IC_RISINGCLR 0x78
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#define IC_FALLINGRD 0x7C
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#define IC_FALLINGCLR 0x7C
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#define IC_TESTBIT 0x80
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static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type);
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/* NOTE on interrupt priorities: The original writers of this code said:
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@ -221,89 +251,101 @@ struct au1xxx_irqmap au1200_irqmap[] __initdata = {
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static void au1x_ic0_unmask(struct irq_data *d)
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{
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unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;
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au_writel(1 << bit, IC0_MASKSET);
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au_writel(1 << bit, IC0_WAKESET);
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au_sync();
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void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
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__raw_writel(1 << bit, base + IC_MASKSET);
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__raw_writel(1 << bit, base + IC_WAKESET);
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wmb();
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}
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static void au1x_ic1_unmask(struct irq_data *d)
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{
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unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;
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au_writel(1 << bit, IC1_MASKSET);
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au_writel(1 << bit, IC1_WAKESET);
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void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR);
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__raw_writel(1 << bit, base + IC_MASKSET);
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__raw_writel(1 << bit, base + IC_WAKESET);
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/* very hacky. does the pb1000 cpld auto-disable this int?
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* nowhere in the current kernel sources is it disabled. --mlau
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*/
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#if defined(CONFIG_MIPS_PB1000)
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if (d->irq == AU1000_GPIO15_INT)
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au_writel(0x4000, PB1000_MDR); /* enable int */
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__raw_writel(0x4000, (void __iomem *)PB1000_MDR); /* enable int */
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#endif
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au_sync();
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wmb();
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}
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static void au1x_ic0_mask(struct irq_data *d)
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{
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unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;
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au_writel(1 << bit, IC0_MASKCLR);
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au_writel(1 << bit, IC0_WAKECLR);
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au_sync();
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void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
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__raw_writel(1 << bit, base + IC_MASKCLR);
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__raw_writel(1 << bit, base + IC_WAKECLR);
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wmb();
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}
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static void au1x_ic1_mask(struct irq_data *d)
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{
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unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;
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au_writel(1 << bit, IC1_MASKCLR);
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au_writel(1 << bit, IC1_WAKECLR);
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au_sync();
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void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR);
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__raw_writel(1 << bit, base + IC_MASKCLR);
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__raw_writel(1 << bit, base + IC_WAKECLR);
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wmb();
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}
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static void au1x_ic0_ack(struct irq_data *d)
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{
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unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;
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void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
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/*
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* This may assume that we don't get interrupts from
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* both edges at once, or if we do, that we don't care.
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*/
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au_writel(1 << bit, IC0_FALLINGCLR);
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au_writel(1 << bit, IC0_RISINGCLR);
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au_sync();
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__raw_writel(1 << bit, base + IC_FALLINGCLR);
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__raw_writel(1 << bit, base + IC_RISINGCLR);
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wmb();
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}
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static void au1x_ic1_ack(struct irq_data *d)
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{
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unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;
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void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR);
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/*
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* This may assume that we don't get interrupts from
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* both edges at once, or if we do, that we don't care.
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*/
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au_writel(1 << bit, IC1_FALLINGCLR);
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au_writel(1 << bit, IC1_RISINGCLR);
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au_sync();
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__raw_writel(1 << bit, base + IC_FALLINGCLR);
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__raw_writel(1 << bit, base + IC_RISINGCLR);
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wmb();
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}
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static void au1x_ic0_maskack(struct irq_data *d)
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{
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unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;
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void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
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au_writel(1 << bit, IC0_WAKECLR);
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au_writel(1 << bit, IC0_MASKCLR);
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au_writel(1 << bit, IC0_RISINGCLR);
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au_writel(1 << bit, IC0_FALLINGCLR);
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au_sync();
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__raw_writel(1 << bit, base + IC_WAKECLR);
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__raw_writel(1 << bit, base + IC_MASKCLR);
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__raw_writel(1 << bit, base + IC_RISINGCLR);
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__raw_writel(1 << bit, base + IC_FALLINGCLR);
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wmb();
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}
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static void au1x_ic1_maskack(struct irq_data *d)
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{
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unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;
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void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR);
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au_writel(1 << bit, IC1_WAKECLR);
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au_writel(1 << bit, IC1_MASKCLR);
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au_writel(1 << bit, IC1_RISINGCLR);
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au_writel(1 << bit, IC1_FALLINGCLR);
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au_sync();
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__raw_writel(1 << bit, base + IC_WAKECLR);
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__raw_writel(1 << bit, base + IC_MASKCLR);
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__raw_writel(1 << bit, base + IC_RISINGCLR);
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__raw_writel(1 << bit, base + IC_FALLINGCLR);
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wmb();
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}
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static int au1x_ic1_setwake(struct irq_data *d, unsigned int on)
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@ -318,13 +360,13 @@ static int au1x_ic1_setwake(struct irq_data *d, unsigned int on)
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return -EINVAL;
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local_irq_save(flags);
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wakemsk = au_readl(SYS_WAKEMSK);
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wakemsk = __raw_readl((void __iomem *)SYS_WAKEMSK);
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if (on)
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wakemsk |= 1 << bit;
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else
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wakemsk &= ~(1 << bit);
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au_writel(wakemsk, SYS_WAKEMSK);
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au_sync();
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__raw_writel(wakemsk, (void __iomem *)SYS_WAKEMSK);
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wmb();
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local_irq_restore(flags);
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return 0;
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@ -356,81 +398,74 @@ static struct irq_chip au1x_ic1_chip = {
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static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type)
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{
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struct irq_chip *chip;
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unsigned long icr[6];
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unsigned int bit, ic, irq = d->irq;
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unsigned int bit, irq = d->irq;
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irq_flow_handler_t handler = NULL;
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unsigned char *name = NULL;
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void __iomem *base;
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int ret;
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if (irq >= AU1000_INTC1_INT_BASE) {
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bit = irq - AU1000_INTC1_INT_BASE;
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chip = &au1x_ic1_chip;
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ic = 1;
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base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR);
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} else {
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bit = irq - AU1000_INTC0_INT_BASE;
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chip = &au1x_ic0_chip;
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ic = 0;
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base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
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}
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if (bit > 31)
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return -EINVAL;
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icr[0] = ic ? IC1_CFG0SET : IC0_CFG0SET;
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icr[1] = ic ? IC1_CFG1SET : IC0_CFG1SET;
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icr[2] = ic ? IC1_CFG2SET : IC0_CFG2SET;
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icr[3] = ic ? IC1_CFG0CLR : IC0_CFG0CLR;
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icr[4] = ic ? IC1_CFG1CLR : IC0_CFG1CLR;
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icr[5] = ic ? IC1_CFG2CLR : IC0_CFG2CLR;
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ret = 0;
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switch (flow_type) { /* cfgregs 2:1:0 */
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case IRQ_TYPE_EDGE_RISING: /* 0:0:1 */
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au_writel(1 << bit, icr[5]);
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au_writel(1 << bit, icr[4]);
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au_writel(1 << bit, icr[0]);
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__raw_writel(1 << bit, base + IC_CFG2CLR);
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__raw_writel(1 << bit, base + IC_CFG1CLR);
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__raw_writel(1 << bit, base + IC_CFG0SET);
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handler = handle_edge_irq;
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name = "riseedge";
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break;
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case IRQ_TYPE_EDGE_FALLING: /* 0:1:0 */
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au_writel(1 << bit, icr[5]);
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au_writel(1 << bit, icr[1]);
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au_writel(1 << bit, icr[3]);
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__raw_writel(1 << bit, base + IC_CFG2CLR);
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__raw_writel(1 << bit, base + IC_CFG1SET);
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__raw_writel(1 << bit, base + IC_CFG0CLR);
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handler = handle_edge_irq;
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name = "falledge";
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break;
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case IRQ_TYPE_EDGE_BOTH: /* 0:1:1 */
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au_writel(1 << bit, icr[5]);
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au_writel(1 << bit, icr[1]);
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au_writel(1 << bit, icr[0]);
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__raw_writel(1 << bit, base + IC_CFG2CLR);
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__raw_writel(1 << bit, base + IC_CFG1SET);
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__raw_writel(1 << bit, base + IC_CFG0SET);
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handler = handle_edge_irq;
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name = "bothedge";
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break;
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case IRQ_TYPE_LEVEL_HIGH: /* 1:0:1 */
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au_writel(1 << bit, icr[2]);
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au_writel(1 << bit, icr[4]);
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au_writel(1 << bit, icr[0]);
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__raw_writel(1 << bit, base + IC_CFG2SET);
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__raw_writel(1 << bit, base + IC_CFG1CLR);
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__raw_writel(1 << bit, base + IC_CFG0SET);
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handler = handle_level_irq;
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name = "hilevel";
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break;
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case IRQ_TYPE_LEVEL_LOW: /* 1:1:0 */
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au_writel(1 << bit, icr[2]);
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au_writel(1 << bit, icr[1]);
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au_writel(1 << bit, icr[3]);
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__raw_writel(1 << bit, base + IC_CFG2SET);
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__raw_writel(1 << bit, base + IC_CFG1SET);
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__raw_writel(1 << bit, base + IC_CFG0CLR);
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handler = handle_level_irq;
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name = "lowlevel";
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break;
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case IRQ_TYPE_NONE: /* 0:0:0 */
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au_writel(1 << bit, icr[5]);
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au_writel(1 << bit, icr[4]);
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au_writel(1 << bit, icr[3]);
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__raw_writel(1 << bit, base + IC_CFG2CLR);
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__raw_writel(1 << bit, base + IC_CFG1CLR);
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__raw_writel(1 << bit, base + IC_CFG0CLR);
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break;
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default:
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ret = -EINVAL;
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}
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__irq_set_chip_handler_name_locked(d->irq, chip, handler, name);
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au_sync();
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wmb();
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return ret;
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}
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@ -444,21 +479,21 @@ asmlinkage void plat_irq_dispatch(void)
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off = MIPS_CPU_IRQ_BASE + 7;
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goto handle;
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} else if (pending & CAUSEF_IP2) {
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s = IC0_REQ0INT;
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s = KSEG1ADDR(AU1000_IC0_PHYS_ADDR) + IC_REQ0INT;
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off = AU1000_INTC0_INT_BASE;
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} else if (pending & CAUSEF_IP3) {
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s = IC0_REQ1INT;
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s = KSEG1ADDR(AU1000_IC0_PHYS_ADDR) + IC_REQ1INT;
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off = AU1000_INTC0_INT_BASE;
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} else if (pending & CAUSEF_IP4) {
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s = IC1_REQ0INT;
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s = KSEG1ADDR(AU1000_IC1_PHYS_ADDR) + IC_REQ0INT;
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off = AU1000_INTC1_INT_BASE;
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} else if (pending & CAUSEF_IP5) {
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s = IC1_REQ1INT;
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s = KSEG1ADDR(AU1000_IC1_PHYS_ADDR) + IC_REQ1INT;
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off = AU1000_INTC1_INT_BASE;
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} else
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goto spurious;
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s = au_readl(s);
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s = __raw_readl((void __iomem *)s);
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if (unlikely(!s)) {
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spurious:
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spurious_interrupt();
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@ -469,48 +504,42 @@ asmlinkage void plat_irq_dispatch(void)
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do_IRQ(off);
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}
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static inline void ic_init(void __iomem *base)
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{
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/* initialize interrupt controller to a safe state */
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__raw_writel(0xffffffff, base + IC_CFG0CLR);
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__raw_writel(0xffffffff, base + IC_CFG1CLR);
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__raw_writel(0xffffffff, base + IC_CFG2CLR);
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__raw_writel(0xffffffff, base + IC_MASKCLR);
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__raw_writel(0xffffffff, base + IC_ASSIGNCLR);
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__raw_writel(0xffffffff, base + IC_WAKECLR);
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__raw_writel(0xffffffff, base + IC_SRCSET);
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__raw_writel(0xffffffff, base + IC_FALLINGCLR);
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__raw_writel(0xffffffff, base + IC_RISINGCLR);
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__raw_writel(0x00000000, base + IC_TESTBIT);
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wmb();
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}
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static void __init au1000_init_irq(struct au1xxx_irqmap *map)
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{
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unsigned int bit, irq_nr;
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int i;
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/*
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* Initialize interrupt controllers to a safe state.
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*/
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au_writel(0xffffffff, IC0_CFG0CLR);
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au_writel(0xffffffff, IC0_CFG1CLR);
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au_writel(0xffffffff, IC0_CFG2CLR);
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au_writel(0xffffffff, IC0_MASKCLR);
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au_writel(0xffffffff, IC0_ASSIGNCLR);
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au_writel(0xffffffff, IC0_WAKECLR);
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au_writel(0xffffffff, IC0_SRCSET);
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au_writel(0xffffffff, IC0_FALLINGCLR);
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au_writel(0xffffffff, IC0_RISINGCLR);
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au_writel(0x00000000, IC0_TESTBIT);
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au_writel(0xffffffff, IC1_CFG0CLR);
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au_writel(0xffffffff, IC1_CFG1CLR);
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au_writel(0xffffffff, IC1_CFG2CLR);
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au_writel(0xffffffff, IC1_MASKCLR);
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au_writel(0xffffffff, IC1_ASSIGNCLR);
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au_writel(0xffffffff, IC1_WAKECLR);
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au_writel(0xffffffff, IC1_SRCSET);
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au_writel(0xffffffff, IC1_FALLINGCLR);
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au_writel(0xffffffff, IC1_RISINGCLR);
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au_writel(0x00000000, IC1_TESTBIT);
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void __iomem *base;
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ic_init((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR));
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ic_init((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR));
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mips_cpu_irq_init();
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/* register all 64 possible IC0+IC1 irq sources as type "none".
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* Use set_irq_type() to set edge/level behaviour at runtime.
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*/
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for (i = AU1000_INTC0_INT_BASE;
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(i < AU1000_INTC0_INT_BASE + 32); i++)
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au1x_ic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE);
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for (irq_nr = AU1000_INTC0_INT_BASE;
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(irq_nr < AU1000_INTC0_INT_BASE + 32); irq_nr++)
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au1x_ic_settype(irq_get_irq_data(irq_nr), IRQ_TYPE_NONE);
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for (i = AU1000_INTC1_INT_BASE;
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(i < AU1000_INTC1_INT_BASE + 32); i++)
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au1x_ic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE);
|
||||
for (irq_nr = AU1000_INTC1_INT_BASE;
|
||||
(irq_nr < AU1000_INTC1_INT_BASE + 32); irq_nr++)
|
||||
au1x_ic_settype(irq_get_irq_data(irq_nr), IRQ_TYPE_NONE);
|
||||
|
||||
/*
|
||||
* Initialize IC0, which is fixed per processor.
|
||||
@ -520,13 +549,13 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map)
|
||||
|
||||
if (irq_nr >= AU1000_INTC1_INT_BASE) {
|
||||
bit = irq_nr - AU1000_INTC1_INT_BASE;
|
||||
if (map->im_request)
|
||||
au_writel(1 << bit, IC1_ASSIGNSET);
|
||||
base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR);
|
||||
} else {
|
||||
bit = irq_nr - AU1000_INTC0_INT_BASE;
|
||||
if (map->im_request)
|
||||
au_writel(1 << bit, IC0_ASSIGNSET);
|
||||
base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
|
||||
}
|
||||
if (map->im_request)
|
||||
__raw_writel(1 << bit, base + IC_ASSIGNSET);
|
||||
|
||||
au1x_ic_settype(irq_get_irq_data(irq_nr), map->im_type);
|
||||
++map;
|
||||
@ -583,17 +612,8 @@ static int alchemy_ic_resume(struct sys_device *dev)
|
||||
struct alchemy_ic_sysdev *icdev =
|
||||
container_of(dev, struct alchemy_ic_sysdev, sysdev);
|
||||
|
||||
__raw_writel(0xffffffff, icdev->base + IC_MASKCLR);
|
||||
__raw_writel(0xffffffff, icdev->base + IC_CFG0CLR);
|
||||
__raw_writel(0xffffffff, icdev->base + IC_CFG1CLR);
|
||||
__raw_writel(0xffffffff, icdev->base + IC_CFG2CLR);
|
||||
__raw_writel(0xffffffff, icdev->base + IC_SRCCLR);
|
||||
__raw_writel(0xffffffff, icdev->base + IC_ASSIGNCLR);
|
||||
__raw_writel(0xffffffff, icdev->base + IC_WAKECLR);
|
||||
__raw_writel(0xffffffff, icdev->base + IC_RISINGCLR);
|
||||
__raw_writel(0xffffffff, icdev->base + IC_FALLINGCLR);
|
||||
__raw_writel(0x00000000, icdev->base + IC_TESTBIT);
|
||||
wmb();
|
||||
ic_init(icdev->base);
|
||||
|
||||
__raw_writel(icdev->pmdata[0], icdev->base + IC_CFG0SET);
|
||||
__raw_writel(icdev->pmdata[1], icdev->base + IC_CFG1SET);
|
||||
__raw_writel(icdev->pmdata[2], icdev->base + IC_CFG2SET);
|
||||
@ -617,7 +637,7 @@ static struct sysdev_class alchemy_ic_sysdev_class = {
|
||||
static int __init alchemy_ic_sysdev_init(void)
|
||||
{
|
||||
struct alchemy_ic_sysdev *icdev;
|
||||
unsigned long icbase[2] = { IC0_PHYS_ADDR, IC1_PHYS_ADDR };
|
||||
unsigned long icbase[2] = { AU1000_IC0_PHYS_ADDR, AU1000_IC1_PHYS_ADDR };
|
||||
int err, i;
|
||||
|
||||
err = sysdev_class_register(&alchemy_ic_sysdev_class);
|
||||
|
||||
@ -630,8 +630,13 @@ enum soc_au1200_ints {
|
||||
|
||||
/*
|
||||
* Physical base addresses for integrated peripherals
|
||||
* 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200
|
||||
*/
|
||||
|
||||
#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
|
||||
#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
|
||||
|
||||
|
||||
#ifdef CONFIG_SOC_AU1000
|
||||
#define MEM_PHYS_ADDR 0x14000000
|
||||
#define STATIC_MEM_PHYS_ADDR 0x14001000
|
||||
@ -643,8 +648,6 @@ enum soc_au1200_ints {
|
||||
#define DMA5_PHYS_ADDR 0x14002500
|
||||
#define DMA6_PHYS_ADDR 0x14002600
|
||||
#define DMA7_PHYS_ADDR 0x14002700
|
||||
#define IC0_PHYS_ADDR 0x10400000
|
||||
#define IC1_PHYS_ADDR 0x11800000
|
||||
#define AC97_PHYS_ADDR 0x10000000
|
||||
#define USBH_PHYS_ADDR 0x10100000
|
||||
#define USBD_PHYS_ADDR 0x10200000
|
||||
@ -680,8 +683,6 @@ enum soc_au1200_ints {
|
||||
#define DMA5_PHYS_ADDR 0x14002500
|
||||
#define DMA6_PHYS_ADDR 0x14002600
|
||||
#define DMA7_PHYS_ADDR 0x14002700
|
||||
#define IC0_PHYS_ADDR 0x10400000
|
||||
#define IC1_PHYS_ADDR 0x11800000
|
||||
#define AC97_PHYS_ADDR 0x10000000
|
||||
#define USBH_PHYS_ADDR 0x10100000
|
||||
#define USBD_PHYS_ADDR 0x10200000
|
||||
@ -718,10 +719,8 @@ enum soc_au1200_ints {
|
||||
#define DMA5_PHYS_ADDR 0x14002500
|
||||
#define DMA6_PHYS_ADDR 0x14002600
|
||||
#define DMA7_PHYS_ADDR 0x14002700
|
||||
#define IC0_PHYS_ADDR 0x10400000
|
||||
#define SD0_PHYS_ADDR 0x10600000
|
||||
#define SD1_PHYS_ADDR 0x10680000
|
||||
#define IC1_PHYS_ADDR 0x11800000
|
||||
#define AC97_PHYS_ADDR 0x10000000
|
||||
#define USBH_PHYS_ADDR 0x10100000
|
||||
#define USBD_PHYS_ADDR 0x10200000
|
||||
@ -749,8 +748,6 @@ enum soc_au1200_ints {
|
||||
#ifdef CONFIG_SOC_AU1550
|
||||
#define MEM_PHYS_ADDR 0x14000000
|
||||
#define STATIC_MEM_PHYS_ADDR 0x14001000
|
||||
#define IC0_PHYS_ADDR 0x10400000
|
||||
#define IC1_PHYS_ADDR 0x11800000
|
||||
#define USBH_PHYS_ADDR 0x14020000
|
||||
#define USBD_PHYS_ADDR 0x10200000
|
||||
#define PCI_PHYS_ADDR 0x14005000
|
||||
@ -786,8 +783,6 @@ enum soc_au1200_ints {
|
||||
#define STATIC_MEM_PHYS_ADDR 0x14001000
|
||||
#define AES_PHYS_ADDR 0x10300000
|
||||
#define CIM_PHYS_ADDR 0x14004000
|
||||
#define IC0_PHYS_ADDR 0x10400000
|
||||
#define IC1_PHYS_ADDR 0x11800000
|
||||
#define USBM_PHYS_ADDR 0x14020000
|
||||
#define USBH_PHYS_ADDR 0x14020100
|
||||
#define UART0_PHYS_ADDR 0x11100000
|
||||
@ -835,112 +830,6 @@ enum soc_au1200_ints {
|
||||
#endif
|
||||
|
||||
|
||||
/* Interrupt Controller register offsets */
|
||||
#define IC_CFG0RD 0x40
|
||||
#define IC_CFG0SET 0x40
|
||||
#define IC_CFG0CLR 0x44
|
||||
#define IC_CFG1RD 0x48
|
||||
#define IC_CFG1SET 0x48
|
||||
#define IC_CFG1CLR 0x4C
|
||||
#define IC_CFG2RD 0x50
|
||||
#define IC_CFG2SET 0x50
|
||||
#define IC_CFG2CLR 0x54
|
||||
#define IC_REQ0INT 0x54
|
||||
#define IC_SRCRD 0x58
|
||||
#define IC_SRCSET 0x58
|
||||
#define IC_SRCCLR 0x5C
|
||||
#define IC_REQ1INT 0x5C
|
||||
#define IC_ASSIGNRD 0x60
|
||||
#define IC_ASSIGNSET 0x60
|
||||
#define IC_ASSIGNCLR 0x64
|
||||
#define IC_WAKERD 0x68
|
||||
#define IC_WAKESET 0x68
|
||||
#define IC_WAKECLR 0x6C
|
||||
#define IC_MASKRD 0x70
|
||||
#define IC_MASKSET 0x70
|
||||
#define IC_MASKCLR 0x74
|
||||
#define IC_RISINGRD 0x78
|
||||
#define IC_RISINGCLR 0x78
|
||||
#define IC_FALLINGRD 0x7C
|
||||
#define IC_FALLINGCLR 0x7C
|
||||
#define IC_TESTBIT 0x80
|
||||
|
||||
|
||||
/* Interrupt Controller 0 */
|
||||
#define IC0_CFG0RD 0xB0400040
|
||||
#define IC0_CFG0SET 0xB0400040
|
||||
#define IC0_CFG0CLR 0xB0400044
|
||||
|
||||
#define IC0_CFG1RD 0xB0400048
|
||||
#define IC0_CFG1SET 0xB0400048
|
||||
#define IC0_CFG1CLR 0xB040004C
|
||||
|
||||
#define IC0_CFG2RD 0xB0400050
|
||||
#define IC0_CFG2SET 0xB0400050
|
||||
#define IC0_CFG2CLR 0xB0400054
|
||||
|
||||
#define IC0_REQ0INT 0xB0400054
|
||||
#define IC0_SRCRD 0xB0400058
|
||||
#define IC0_SRCSET 0xB0400058
|
||||
#define IC0_SRCCLR 0xB040005C
|
||||
#define IC0_REQ1INT 0xB040005C
|
||||
|
||||
#define IC0_ASSIGNRD 0xB0400060
|
||||
#define IC0_ASSIGNSET 0xB0400060
|
||||
#define IC0_ASSIGNCLR 0xB0400064
|
||||
|
||||
#define IC0_WAKERD 0xB0400068
|
||||
#define IC0_WAKESET 0xB0400068
|
||||
#define IC0_WAKECLR 0xB040006C
|
||||
|
||||
#define IC0_MASKRD 0xB0400070
|
||||
#define IC0_MASKSET 0xB0400070
|
||||
#define IC0_MASKCLR 0xB0400074
|
||||
|
||||
#define IC0_RISINGRD 0xB0400078
|
||||
#define IC0_RISINGCLR 0xB0400078
|
||||
#define IC0_FALLINGRD 0xB040007C
|
||||
#define IC0_FALLINGCLR 0xB040007C
|
||||
|
||||
#define IC0_TESTBIT 0xB0400080
|
||||
|
||||
/* Interrupt Controller 1 */
|
||||
#define IC1_CFG0RD 0xB1800040
|
||||
#define IC1_CFG0SET 0xB1800040
|
||||
#define IC1_CFG0CLR 0xB1800044
|
||||
|
||||
#define IC1_CFG1RD 0xB1800048
|
||||
#define IC1_CFG1SET 0xB1800048
|
||||
#define IC1_CFG1CLR 0xB180004C
|
||||
|
||||
#define IC1_CFG2RD 0xB1800050
|
||||
#define IC1_CFG2SET 0xB1800050
|
||||
#define IC1_CFG2CLR 0xB1800054
|
||||
|
||||
#define IC1_REQ0INT 0xB1800054
|
||||
#define IC1_SRCRD 0xB1800058
|
||||
#define IC1_SRCSET 0xB1800058
|
||||
#define IC1_SRCCLR 0xB180005C
|
||||
#define IC1_REQ1INT 0xB180005C
|
||||
|
||||
#define IC1_ASSIGNRD 0xB1800060
|
||||
#define IC1_ASSIGNSET 0xB1800060
|
||||
#define IC1_ASSIGNCLR 0xB1800064
|
||||
|
||||
#define IC1_WAKERD 0xB1800068
|
||||
#define IC1_WAKESET 0xB1800068
|
||||
#define IC1_WAKECLR 0xB180006C
|
||||
|
||||
#define IC1_MASKRD 0xB1800070
|
||||
#define IC1_MASKSET 0xB1800070
|
||||
#define IC1_MASKCLR 0xB1800074
|
||||
|
||||
#define IC1_RISINGRD 0xB1800078
|
||||
#define IC1_RISINGCLR 0xB1800078
|
||||
#define IC1_FALLINGRD 0xB180007C
|
||||
#define IC1_FALLINGCLR 0xB180007C
|
||||
|
||||
#define IC1_TESTBIT 0xB1800080
|
||||
|
||||
|
||||
/* Au1000 */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user