forked from luck/tmp_suning_uos_patched
Pull lameter-spinlock-optimization into release branch
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commit
dcf8296216
@ -93,7 +93,15 @@ _raw_spin_lock_flags (spinlock_t *lock, unsigned long flags)
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# endif /* CONFIG_MCKINLEY */
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#endif
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}
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#define _raw_spin_lock(lock) _raw_spin_lock_flags(lock, 0)
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/* Unlock by doing an ordered store and releasing the cacheline with nta */
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static inline void _raw_spin_unlock(spinlock_t *x) {
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barrier();
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asm volatile ("st4.rel.nta [%0] = r0\n\t" :: "r"(x));
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}
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#else /* !ASM_SUPPORTED */
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#define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
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# define _raw_spin_lock(x) \
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@ -109,16 +117,16 @@ do { \
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} while (ia64_spinlock_val); \
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} \
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} while (0)
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#define _raw_spin_unlock(x) do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0)
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#endif /* !ASM_SUPPORTED */
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#define spin_is_locked(x) ((x)->lock != 0)
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#define _raw_spin_unlock(x) do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0)
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#define _raw_spin_trylock(x) (cmpxchg_acq(&(x)->lock, 0, 1) == 0)
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#define spin_unlock_wait(x) do { barrier(); } while ((x)->lock)
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typedef struct {
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volatile unsigned int read_counter : 31;
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volatile unsigned int write_lock : 1;
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volatile unsigned int read_counter : 24;
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volatile unsigned int write_lock : 8;
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#ifdef CONFIG_PREEMPT
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unsigned int break_lock;
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#endif
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@ -174,6 +182,13 @@ do { \
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(result == 0); \
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})
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static inline void _raw_write_unlock(rwlock_t *x)
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{
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u8 *y = (u8 *)x;
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barrier();
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asm volatile ("st1.rel.nta [%0] = r0\n\t" :: "r"(y+3) : "memory" );
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}
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#else /* !ASM_SUPPORTED */
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#define _raw_write_lock(l) \
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@ -195,14 +210,14 @@ do { \
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(ia64_val == 0); \
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})
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static inline void _raw_write_unlock(rwlock_t *x)
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{
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barrier();
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x->write_lock = 0;
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}
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#endif /* !ASM_SUPPORTED */
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#define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
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#define _raw_write_unlock(x) \
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({ \
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smp_mb__before_clear_bit(); /* need barrier before releasing lock... */ \
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clear_bit(31, (x)); \
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})
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#endif /* _ASM_IA64_SPINLOCK_H */
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