forked from luck/tmp_suning_uos_patched
csky/ftrace: Fixup ftrace_modify_code deadlock without CPU_HAS_ICACHE_INS
If ICACHE_INS is not supported, we use IPI to sync icache on each core. But ftrace_modify_code is called from stop_machine from default implementation of arch_ftrace_update_code and stop_machine callback is irq_disabled. When you call ipi with irq_disabled, a deadlock will happen. We couldn't use icache_flush with irq_disabled, but startup make_nop is specific case and it needn't ipi other cores. Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
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@ -3,6 +3,7 @@
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#include <linux/ftrace.h>
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#include <linux/uaccess.h>
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#include <linux/stop_machine.h>
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#include <asm/cacheflush.h>
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#ifdef CONFIG_DYNAMIC_FTRACE
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@ -201,5 +202,35 @@ int ftrace_disable_ftrace_graph_caller(void)
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#endif /* CONFIG_DYNAMIC_FTRACE */
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#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
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#ifndef CONFIG_CPU_HAS_ICACHE_INS
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struct ftrace_modify_param {
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int command;
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atomic_t cpu_count;
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};
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static int __ftrace_modify_code(void *data)
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{
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struct ftrace_modify_param *param = data;
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if (atomic_inc_return(¶m->cpu_count) == 1) {
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ftrace_modify_all_code(param->command);
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atomic_inc(¶m->cpu_count);
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} else {
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while (atomic_read(¶m->cpu_count) <= num_online_cpus())
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cpu_relax();
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local_icache_inv_all(NULL);
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}
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return 0;
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}
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void arch_ftrace_update_code(int command)
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{
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struct ftrace_modify_param param = { command, ATOMIC_INIT(0) };
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stop_machine(__ftrace_modify_code, ¶m, cpu_online_mask);
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}
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#endif
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/* _mcount is defined in abi's mcount.S */
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EXPORT_SYMBOL(_mcount);
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@ -7,8 +7,12 @@
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#include <asm/cache.h>
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#include <asm/barrier.h>
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/* for L1-cache */
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#define INS_CACHE (1 << 0)
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#define DATA_CACHE (1 << 1)
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#define CACHE_INV (1 << 4)
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#define CACHE_CLR (1 << 5)
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#define CACHE_OMS (1 << 6)
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void local_icache_inv_all(void *priv)
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{
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@ -16,11 +20,6 @@ void local_icache_inv_all(void *priv)
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sync_is();
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}
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void icache_inv_all(void)
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{
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on_each_cpu(local_icache_inv_all, NULL, 1);
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}
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#ifdef CONFIG_CPU_HAS_ICACHE_INS
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void icache_inv_range(unsigned long start, unsigned long end)
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{
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@ -31,9 +30,43 @@ void icache_inv_range(unsigned long start, unsigned long end)
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sync_is();
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}
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#else
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struct cache_range {
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unsigned long start;
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unsigned long end;
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};
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static DEFINE_SPINLOCK(cache_lock);
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static inline void cache_op_line(unsigned long i, unsigned int val)
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{
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mtcr("cr22", i);
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mtcr("cr17", val);
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}
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void local_icache_inv_range(void *priv)
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{
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struct cache_range *param = priv;
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unsigned long i = param->start & ~(L1_CACHE_BYTES - 1);
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unsigned long flags;
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spin_lock_irqsave(&cache_lock, flags);
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for (; i < param->end; i += L1_CACHE_BYTES)
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cache_op_line(i, INS_CACHE | CACHE_INV | CACHE_OMS);
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spin_unlock_irqrestore(&cache_lock, flags);
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sync_is();
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}
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void icache_inv_range(unsigned long start, unsigned long end)
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{
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icache_inv_all();
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struct cache_range param = { start, end };
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if (irqs_disabled())
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local_icache_inv_range(¶m);
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else
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on_each_cpu(local_icache_inv_range, ¶m, 1);
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}
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#endif
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