forked from luck/tmp_suning_uos_patched
[POWERPC] ps3: add spu support
Adds spu support for the PS3 platform. Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
This commit is contained in:
Geoff Levand
Paul Mackerras
parent
00a3e2e93c
commit
de91a53429
@ -1,2 +1,4 @@
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obj-y += setup.o mm.o smp.o time.o hvcall.o htab.o repository.o
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obj-y += interrupt.o exports.o os-area.o
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obj-$(CONFIG_SPU_BASE) += spu.o
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@ -57,4 +57,12 @@ int ps3_set_rtc_time(struct rtc_time *time);
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int __init ps3_os_area_init(void);
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u64 ps3_os_area_rtc_diff(void);
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/* spu */
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#if defined(CONFIG_SPU_BASE)
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void ps3_spu_set_platform (void);
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#else
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static inline void ps3_spu_set_platform (void) {}
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#endif
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#endif
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613
arch/powerpc/platforms/ps3/spu.c
Normal file
613
arch/powerpc/platforms/ps3/spu.c
Normal file
@ -0,0 +1,613 @@
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/*
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* PS3 Platform spu routines.
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*
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* Copyright (C) 2006 Sony Computer Entertainment Inc.
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* Copyright 2006 Sony Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mmzone.h>
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <asm/spu.h>
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#include <asm/spu_priv1.h>
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#include <asm/ps3.h>
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#include <asm/lv1call.h>
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/* spu_management_ops */
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/**
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* enum spe_type - Type of spe to create.
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* @spe_type_logical: Standard logical spe.
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*
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* For use with lv1_construct_logical_spe(). The current HV does not support
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* any types other than those listed.
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*/
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enum spe_type {
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SPE_TYPE_LOGICAL = 0,
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};
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/**
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* struct spe_shadow - logical spe shadow register area.
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*
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* Read-only shadow of spe registers.
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*/
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struct spe_shadow {
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u8 padding_0000[0x0140];
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u64 int_status_class0_RW; /* 0x0140 */
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u64 int_status_class1_RW; /* 0x0148 */
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u64 int_status_class2_RW; /* 0x0150 */
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u8 padding_0158[0x0610-0x0158];
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u64 mfc_dsisr_RW; /* 0x0610 */
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u8 padding_0618[0x0620-0x0618];
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u64 mfc_dar_RW; /* 0x0620 */
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u8 padding_0628[0x0800-0x0628];
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u64 mfc_dsipr_R; /* 0x0800 */
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u8 padding_0808[0x0810-0x0808];
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u64 mfc_lscrr_R; /* 0x0810 */
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u8 padding_0818[0x0c00-0x0818];
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u64 mfc_cer_R; /* 0x0c00 */
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u8 padding_0c08[0x0f00-0x0c08];
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u64 spe_execution_status; /* 0x0f00 */
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u8 padding_0f08[0x1000-0x0f08];
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} __attribute__ ((packed));
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/**
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* enum spe_ex_state - Logical spe execution state.
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* @spe_ex_state_unexecutable: Uninitialized.
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* @spe_ex_state_executable: Enabled, not ready.
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* @spe_ex_state_executed: Ready for use.
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*
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* The execution state (status) of the logical spe as reported in
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* struct spe_shadow:spe_execution_status.
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*/
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enum spe_ex_state {
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SPE_EX_STATE_UNEXECUTABLE = 0,
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SPE_EX_STATE_EXECUTABLE = 2,
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SPE_EX_STATE_EXECUTED = 3,
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};
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/**
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* struct priv1_cache - Cached values of priv1 registers.
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* @masks[]: Array of cached spe interrupt masks, indexed by class.
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* @sr1: Cached mfc_sr1 register.
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* @tclass_id: Cached mfc_tclass_id register.
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*/
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struct priv1_cache {
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u64 masks[3];
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u64 sr1;
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u64 tclass_id;
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};
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/**
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* struct spu_pdata - Platform state variables.
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* @spe_id: HV spe id returned by lv1_construct_logical_spe().
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* @resource_id: HV spe resource id returned by
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* ps3_repository_read_spe_resource_id().
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* @priv2_addr: lpar address of spe priv2 area returned by
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* lv1_construct_logical_spe().
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* @shadow_addr: lpar address of spe register shadow area returned by
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* lv1_construct_logical_spe().
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* @shadow: Virtual (ioremap) address of spe register shadow area.
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* @cache: Cached values of priv1 registers.
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*/
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struct spu_pdata {
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u64 spe_id;
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u64 resource_id;
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u64 priv2_addr;
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u64 shadow_addr;
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struct spe_shadow __iomem *shadow;
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struct priv1_cache cache;
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};
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static struct spu_pdata *spu_pdata(struct spu *spu)
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{
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return spu->pdata;
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}
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#define dump_areas(_a, _b, _c, _d, _e) \
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_dump_areas(_a, _b, _c, _d, _e, __func__, __LINE__)
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static void _dump_areas(unsigned int spe_id, unsigned long priv2,
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unsigned long problem, unsigned long ls, unsigned long shadow,
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const char* func, int line)
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{
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pr_debug("%s:%d: spe_id: %xh (%u)\n", func, line, spe_id, spe_id);
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pr_debug("%s:%d: priv2: %lxh\n", func, line, priv2);
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pr_debug("%s:%d: problem: %lxh\n", func, line, problem);
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pr_debug("%s:%d: ls: %lxh\n", func, line, ls);
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pr_debug("%s:%d: shadow: %lxh\n", func, line, shadow);
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}
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static unsigned long get_vas_id(void)
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{
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unsigned long id;
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lv1_get_logical_ppe_id(&id);
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lv1_get_virtual_address_space_id_of_ppe(id, &id);
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return id;
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}
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static int __init construct_spu(struct spu *spu)
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{
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int result;
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unsigned long unused;
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result = lv1_construct_logical_spe(PAGE_SHIFT, PAGE_SHIFT, PAGE_SHIFT,
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PAGE_SHIFT, PAGE_SHIFT, get_vas_id(), SPE_TYPE_LOGICAL,
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&spu_pdata(spu)->priv2_addr, &spu->problem_phys,
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&spu->local_store_phys, &unused,
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&spu_pdata(spu)->shadow_addr,
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&spu_pdata(spu)->spe_id);
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if (result) {
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pr_debug("%s:%d: lv1_construct_logical_spe failed: %s\n",
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__func__, __LINE__, ps3_result(result));
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return result;
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}
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return result;
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}
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static int __init add_spu_pages(unsigned long start_addr, unsigned long size)
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{
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int result;
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unsigned long start_pfn;
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unsigned long nr_pages;
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struct pglist_data *pgdata;
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struct zone *zone;
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BUG_ON(!mem_init_done);
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start_pfn = start_addr >> PAGE_SHIFT;
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nr_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
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pgdata = NODE_DATA(0);
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zone = pgdata->node_zones;
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result = __add_pages(zone, start_pfn, nr_pages);
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if (result)
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pr_debug("%s:%d: __add_pages failed: (%d)\n",
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__func__, __LINE__, result);
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return result;
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}
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static void spu_unmap(struct spu *spu)
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{
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iounmap(spu->priv2);
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iounmap(spu->problem);
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iounmap((__force u8 __iomem *)spu->local_store);
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iounmap(spu_pdata(spu)->shadow);
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}
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static int __init setup_areas(struct spu *spu)
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{
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struct table {char* name; unsigned long addr; unsigned long size;};
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int result;
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/* setup pages */
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result = add_spu_pages(spu->local_store_phys, LS_SIZE);
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if (result)
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goto fail_add;
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result = add_spu_pages(spu->problem_phys, sizeof(struct spu_problem));
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if (result)
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goto fail_add;
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/* ioremap */
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spu_pdata(spu)->shadow = __ioremap(
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spu_pdata(spu)->shadow_addr, sizeof(struct spe_shadow),
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PAGE_READONLY | _PAGE_NO_CACHE | _PAGE_GUARDED);
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if (!spu_pdata(spu)->shadow) {
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pr_debug("%s:%d: ioremap shadow failed\n", __func__, __LINE__);
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goto fail_ioremap;
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}
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spu->local_store = ioremap(spu->local_store_phys, LS_SIZE);
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if (!spu->local_store) {
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pr_debug("%s:%d: ioremap local_store failed\n",
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__func__, __LINE__);
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goto fail_ioremap;
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}
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spu->problem = ioremap(spu->problem_phys,
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sizeof(struct spu_problem));
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if (!spu->problem) {
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pr_debug("%s:%d: ioremap problem failed\n", __func__, __LINE__);
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goto fail_ioremap;
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}
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spu->priv2 = ioremap(spu_pdata(spu)->priv2_addr,
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sizeof(struct spu_priv2));
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if (!spu->priv2) {
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pr_debug("%s:%d: ioremap priv2 failed\n", __func__, __LINE__);
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goto fail_ioremap;
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}
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dump_areas(spu_pdata(spu)->spe_id, spu_pdata(spu)->priv2_addr,
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spu->problem_phys, spu->local_store_phys,
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spu_pdata(spu)->shadow_addr);
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dump_areas(spu_pdata(spu)->spe_id, (unsigned long)spu->priv2,
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(unsigned long)spu->problem, (unsigned long)spu->local_store,
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(unsigned long)spu_pdata(spu)->shadow);
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return 0;
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fail_ioremap:
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spu_unmap(spu);
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fail_add:
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return result;
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}
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static int __init setup_interrupts(struct spu *spu)
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{
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int result;
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result = ps3_alloc_spe_irq(spu_pdata(spu)->spe_id, 0,
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&spu->irqs[0]);
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if (result)
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goto fail_alloc_0;
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result = ps3_alloc_spe_irq(spu_pdata(spu)->spe_id, 1,
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&spu->irqs[1]);
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if (result)
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goto fail_alloc_1;
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result = ps3_alloc_spe_irq(spu_pdata(spu)->spe_id, 2,
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&spu->irqs[2]);
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if (result)
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goto fail_alloc_2;
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return result;
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fail_alloc_2:
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ps3_free_spe_irq(spu->irqs[1]);
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fail_alloc_1:
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ps3_free_spe_irq(spu->irqs[0]);
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fail_alloc_0:
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spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = NO_IRQ;
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return result;
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}
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static int __init enable_spu(struct spu *spu)
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{
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int result;
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result = lv1_enable_logical_spe(spu_pdata(spu)->spe_id,
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spu_pdata(spu)->resource_id);
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if (result) {
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pr_debug("%s:%d: lv1_enable_logical_spe failed: %s\n",
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__func__, __LINE__, ps3_result(result));
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goto fail_enable;
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}
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result = setup_areas(spu);
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if (result)
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goto fail_areas;
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result = setup_interrupts(spu);
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if (result)
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goto fail_interrupts;
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return 0;
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fail_interrupts:
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spu_unmap(spu);
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fail_areas:
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lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
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fail_enable:
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return result;
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}
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static int ps3_destroy_spu(struct spu *spu)
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{
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int result;
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pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);
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result = lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
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BUG_ON(result);
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ps3_free_spe_irq(spu->irqs[2]);
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ps3_free_spe_irq(spu->irqs[1]);
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ps3_free_spe_irq(spu->irqs[0]);
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spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = NO_IRQ;
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spu_unmap(spu);
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result = lv1_destruct_logical_spe(spu_pdata(spu)->spe_id);
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BUG_ON(result);
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kfree(spu->pdata);
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spu->pdata = NULL;
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return 0;
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}
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static int __init ps3_create_spu(struct spu *spu, void *data)
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{
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int result;
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pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);
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spu->pdata = kzalloc(sizeof(struct spu_pdata),
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GFP_KERNEL);
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if (!spu->pdata) {
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result = -ENOMEM;
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goto fail_malloc;
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}
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spu_pdata(spu)->resource_id = (unsigned long)data;
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/* Init cached reg values to HV defaults. */
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spu_pdata(spu)->cache.sr1 = 0x33;
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result = construct_spu(spu);
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if (result)
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goto fail_construct;
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/* For now, just go ahead and enable it. */
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result = enable_spu(spu);
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if (result)
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goto fail_enable;
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/* Make sure the spu is in SPE_EX_STATE_EXECUTED. */
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/* need something better here!!! */
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while (in_be64(&spu_pdata(spu)->shadow->spe_execution_status)
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!= SPE_EX_STATE_EXECUTED)
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(void)0;
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return result;
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fail_enable:
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fail_construct:
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ps3_destroy_spu(spu);
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fail_malloc:
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return result;
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}
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static int __init ps3_enumerate_spus(int (*fn)(void *data))
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{
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int result;
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unsigned int num_resource_id;
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unsigned int i;
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result = ps3_repository_read_num_spu_resource_id(&num_resource_id);
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pr_debug("%s:%d: num_resource_id %u\n", __func__, __LINE__,
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num_resource_id);
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/*
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* For now, just create logical spus equal to the number
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* of physical spus reserved for the partition.
|
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*/
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|
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for (i = 0; i < num_resource_id; i++) {
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enum ps3_spu_resource_type resource_type;
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unsigned int resource_id;
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result = ps3_repository_read_spu_resource_id(i,
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&resource_type, &resource_id);
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|
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if (result)
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break;
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if (resource_type == PS3_SPU_RESOURCE_TYPE_EXCLUSIVE) {
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result = fn((void*)(unsigned long)resource_id);
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if (result)
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break;
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}
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}
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|
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if (result)
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printk(KERN_WARNING "%s:%d: Error initializing spus\n",
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__func__, __LINE__);
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|
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return result;
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}
|
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|
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const struct spu_management_ops spu_management_ps3_ops = {
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.enumerate_spus = ps3_enumerate_spus,
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.create_spu = ps3_create_spu,
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.destroy_spu = ps3_destroy_spu,
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};
|
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|
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/* spu_priv1_ops */
|
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|
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static void int_mask_and(struct spu *spu, int class, u64 mask)
|
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{
|
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u64 old_mask;
|
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|
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/* are these serialized by caller??? */
|
||||
old_mask = spu_int_mask_get(spu, class);
|
||||
spu_int_mask_set(spu, class, old_mask & mask);
|
||||
}
|
||||
|
||||
static void int_mask_or(struct spu *spu, int class, u64 mask)
|
||||
{
|
||||
u64 old_mask;
|
||||
|
||||
old_mask = spu_int_mask_get(spu, class);
|
||||
spu_int_mask_set(spu, class, old_mask | mask);
|
||||
}
|
||||
|
||||
static void int_mask_set(struct spu *spu, int class, u64 mask)
|
||||
{
|
||||
spu_pdata(spu)->cache.masks[class] = mask;
|
||||
lv1_set_spe_interrupt_mask(spu_pdata(spu)->spe_id, class,
|
||||
spu_pdata(spu)->cache.masks[class]);
|
||||
}
|
||||
|
||||
static u64 int_mask_get(struct spu *spu, int class)
|
||||
{
|
||||
return spu_pdata(spu)->cache.masks[class];
|
||||
}
|
||||
|
||||
static void int_stat_clear(struct spu *spu, int class, u64 stat)
|
||||
{
|
||||
/* Note that MFC_DSISR will be cleared when class1[MF] is set. */
|
||||
|
||||
lv1_clear_spe_interrupt_status(spu_pdata(spu)->spe_id, class,
|
||||
stat, 0);
|
||||
}
|
||||
|
||||
static u64 int_stat_get(struct spu *spu, int class)
|
||||
{
|
||||
u64 stat;
|
||||
|
||||
lv1_get_spe_interrupt_status(spu_pdata(spu)->spe_id, class, &stat);
|
||||
return stat;
|
||||
}
|
||||
|
||||
static void cpu_affinity_set(struct spu *spu, int cpu)
|
||||
{
|
||||
/* No support. */
|
||||
}
|
||||
|
||||
static u64 mfc_dar_get(struct spu *spu)
|
||||
{
|
||||
return in_be64(&spu_pdata(spu)->shadow->mfc_dar_RW);
|
||||
}
|
||||
|
||||
static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
|
||||
{
|
||||
/* Nothing to do, cleared in int_stat_clear(). */
|
||||
}
|
||||
|
||||
static u64 mfc_dsisr_get(struct spu *spu)
|
||||
{
|
||||
return in_be64(&spu_pdata(spu)->shadow->mfc_dsisr_RW);
|
||||
}
|
||||
|
||||
static void mfc_sdr_setup(struct spu *spu)
|
||||
{
|
||||
/* Nothing to do. */
|
||||
}
|
||||
|
||||
static void mfc_sr1_set(struct spu *spu, u64 sr1)
|
||||
{
|
||||
/* Check bits allowed by HV. */
|
||||
|
||||
static const u64 allowed = ~(MFC_STATE1_LOCAL_STORAGE_DECODE_MASK
|
||||
| MFC_STATE1_PROBLEM_STATE_MASK);
|
||||
|
||||
BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed));
|
||||
|
||||
spu_pdata(spu)->cache.sr1 = sr1;
|
||||
lv1_set_spe_privilege_state_area_1_register(
|
||||
spu_pdata(spu)->spe_id,
|
||||
offsetof(struct spu_priv1, mfc_sr1_RW),
|
||||
spu_pdata(spu)->cache.sr1);
|
||||
}
|
||||
|
||||
static u64 mfc_sr1_get(struct spu *spu)
|
||||
{
|
||||
return spu_pdata(spu)->cache.sr1;
|
||||
}
|
||||
|
||||
static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
|
||||
{
|
||||
spu_pdata(spu)->cache.tclass_id = tclass_id;
|
||||
lv1_set_spe_privilege_state_area_1_register(
|
||||
spu_pdata(spu)->spe_id,
|
||||
offsetof(struct spu_priv1, mfc_tclass_id_RW),
|
||||
spu_pdata(spu)->cache.tclass_id);
|
||||
}
|
||||
|
||||
static u64 mfc_tclass_id_get(struct spu *spu)
|
||||
{
|
||||
return spu_pdata(spu)->cache.tclass_id;
|
||||
}
|
||||
|
||||
static void tlb_invalidate(struct spu *spu)
|
||||
{
|
||||
/* Nothing to do. */
|
||||
}
|
||||
|
||||
static void resource_allocation_groupID_set(struct spu *spu, u64 id)
|
||||
{
|
||||
/* No support. */
|
||||
}
|
||||
|
||||
static u64 resource_allocation_groupID_get(struct spu *spu)
|
||||
{
|
||||
return 0; /* No support. */
|
||||
}
|
||||
|
||||
static void resource_allocation_enable_set(struct spu *spu, u64 enable)
|
||||
{
|
||||
/* No support. */
|
||||
}
|
||||
|
||||
static u64 resource_allocation_enable_get(struct spu *spu)
|
||||
{
|
||||
return 0; /* No support. */
|
||||
}
|
||||
|
||||
const struct spu_priv1_ops spu_priv1_ps3_ops = {
|
||||
.int_mask_and = int_mask_and,
|
||||
.int_mask_or = int_mask_or,
|
||||
.int_mask_set = int_mask_set,
|
||||
.int_mask_get = int_mask_get,
|
||||
.int_stat_clear = int_stat_clear,
|
||||
.int_stat_get = int_stat_get,
|
||||
.cpu_affinity_set = cpu_affinity_set,
|
||||
.mfc_dar_get = mfc_dar_get,
|
||||
.mfc_dsisr_set = mfc_dsisr_set,
|
||||
.mfc_dsisr_get = mfc_dsisr_get,
|
||||
.mfc_sdr_setup = mfc_sdr_setup,
|
||||
.mfc_sr1_set = mfc_sr1_set,
|
||||
.mfc_sr1_get = mfc_sr1_get,
|
||||
.mfc_tclass_id_set = mfc_tclass_id_set,
|
||||
.mfc_tclass_id_get = mfc_tclass_id_get,
|
||||
.tlb_invalidate = tlb_invalidate,
|
||||
.resource_allocation_groupID_set = resource_allocation_groupID_set,
|
||||
.resource_allocation_groupID_get = resource_allocation_groupID_get,
|
||||
.resource_allocation_enable_set = resource_allocation_enable_set,
|
||||
.resource_allocation_enable_get = resource_allocation_enable_get,
|
||||
};
|
||||
|
||||
void ps3_spu_set_platform(void)
|
||||
{
|
||||
spu_priv1_ops = &spu_priv1_ps3_ops;
|
||||
spu_management_ops = &spu_management_ps3_ops;
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user