forked from luck/tmp_suning_uos_patched
sh: urquell: Handle EXTAL configuration here, too.
urquell happens to use the same mode pins and EXTAL configuration as SDK7786, so just copy it over. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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c809821827
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@ -2,7 +2,7 @@
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* Renesas Technology Corp. SH7786 Urquell Support.
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* Renesas Technology Corp. SH7786 Urquell Support.
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*
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*
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* Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
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* Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
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* Copyright (C) 2009 Paul Mundt
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* Copyright (C) 2009, 2010 Paul Mundt
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*
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*
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* Based on board-sh7785lcr.c
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* Based on board-sh7785lcr.c
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* Copyright (C) 2008 Yoshihiro Shimoda
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* Copyright (C) 2008 Yoshihiro Shimoda
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@ -19,6 +19,7 @@
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#include <linux/delay.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/gpio.h>
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#include <linux/irq.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include <mach/urquell.h>
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#include <mach/urquell.h>
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#include <cpu/sh7786.h>
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#include <cpu/sh7786.h>
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#include <asm/heartbeat.h>
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#include <asm/heartbeat.h>
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@ -175,6 +176,27 @@ static int urquell_mode_pins(void)
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return __raw_readw(UBOARDREG(MDSWMR));
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return __raw_readw(UBOARDREG(MDSWMR));
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}
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}
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static int urquell_clk_init(void)
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{
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struct clk *clk;
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int ret;
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/*
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* Only handle the EXTAL case, anyone interfacing a crystal
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* resonator will need to provide their own input clock.
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*/
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if (test_mode_pin(MODE_PIN9))
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return -EINVAL;
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clk = clk_get(NULL, "extal");
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if (!clk || IS_ERR(clk))
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return PTR_ERR(clk);
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ret = clk_set_rate(clk, 33333333);
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clk_put(clk);
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return ret;
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}
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/* Initialize the board */
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/* Initialize the board */
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static void __init urquell_setup(char **cmdline_p)
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static void __init urquell_setup(char **cmdline_p)
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{
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{
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@ -191,4 +213,5 @@ static struct sh_machine_vector mv_urquell __initmv = {
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.mv_setup = urquell_setup,
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.mv_setup = urquell_setup,
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.mv_init_irq = urquell_init_irq,
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.mv_init_irq = urquell_init_irq,
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.mv_mode_pins = urquell_mode_pins,
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.mv_mode_pins = urquell_mode_pins,
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.mv_clk_init = urquell_clk_init,
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};
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};
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