forked from luck/tmp_suning_uos_patched
pinctrl: sh-pfc: Updates for v4.13 (take two)
- Add SCIF1 and SCIF2 pin groups for R-Car V2H,
- Add EtherAVB, DU parallel RGB output, and PWM pin groups for R-Car
H3 ES2.0,
- Add pin and gpio controller support for RZ/A1.
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Merge tag 'sh-pfc-for-v4.13-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.13 (take two)
- Add SCIF1 and SCIF2 pin groups for R-Car V2H,
- Add EtherAVB, DU parallel RGB output, and PWM pin groups for R-Car
H3 ES2.0,
- Add pin and gpio controller support for RZ/A1.
This commit is contained in:
Linus Walleij
commit
df81b9411a
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@ -0,0 +1,221 @@
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|||
Renesas RZ/A1 combined Pin and GPIO controller
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The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO controller,
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named "Ports" in the hardware reference manual.
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Pin multiplexing and GPIO configuration is performed on a per-pin basis
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writing configuration values to per-port register sets.
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Each "port" features up to 16 pins, each of them configurable for GPIO
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function (port mode) or in alternate function mode.
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Up to 8 different alternate function modes exist for each single pin.
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Pin controller node
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-------------------
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Required properties:
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- compatible
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this shall be "renesas,r7s72100-ports".
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- reg
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address base and length of the memory area where the pin controller
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hardware is mapped to.
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Example:
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Pin controller node for RZ/A1H SoC (r7s72100)
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pinctrl: pin-controller@fcfe3000 {
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compatible = "renesas,r7s72100-ports";
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reg = <0xfcfe3000 0x4230>;
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};
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Sub-nodes
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---------
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The child nodes of the pin controller node describe a pin multiplexing
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function or a GPIO controller alternatively.
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- Pin multiplexing sub-nodes:
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A pin multiplexing sub-node describes how to configure a set of
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(or a single) pin in some desired alternate function mode.
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A single sub-node may define several pin configurations.
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A few alternate function require special pin configuration flags to be
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supplied along with the alternate function configuration number.
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The hardware reference manual specifies when a pin function requires
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"software IO driven" mode to be specified. To do so use the generic
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properties from the <include/linux/pinctrl/pinconf_generic.h> header file
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to instruct the pin controller to perform the desired pin configuration
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operation.
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Please refer to pinctrl-bindings.txt to get to know more on generic
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pin properties usage.
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The allowed generic formats for a pin multiplexing sub-node are the
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following ones:
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node-1 {
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pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
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GENERIC_PINCONFIG;
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};
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node-2 {
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sub-node-1 {
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pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
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GENERIC_PINCONFIG;
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};
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sub-node-2 {
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pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
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GENERIC_PINCONFIG;
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};
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...
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sub-node-n {
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pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
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GENERIC_PINCONFIG;
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};
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};
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Use the second format when pins part of the same logical group need to have
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different generic pin configuration flags applied.
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Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle
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of the most external one.
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Eg.
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client-1 {
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...
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pinctrl-0 = <&node-1>;
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...
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};
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client-2 {
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...
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pinctrl-0 = <&node-2>;
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...
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};
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Required properties:
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- pinmux:
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integer array representing pin number and pin multiplexing configuration.
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When a pin has to be configured in alternate function mode, use this
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property to identify the pin by its global index, and provide its
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alternate function configuration number along with it.
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When multiple pins are required to be configured as part of the same
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alternate function they shall be specified as members of the same
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argument list of a single "pinmux" property.
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Helper macros to ease assembling the pin index from its position
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(port where it sits on and pin number) and alternate function identifier
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are provided by the pin controller header file at:
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<include/dt-bindings/pinctrl/r7s72100-pinctrl.h>
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Integers values in "pinmux" argument list are assembled as:
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((PORT * 16 + PIN) | MUX_FUNC << 16)
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Optional generic properties:
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- input-enable:
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enable input bufer for pins requiring software driven IO input
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operations.
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- output-high:
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enable output buffer for pins requiring software driven IO output
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operations. output-low can be used alternatively, as line value is
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ignored by the driver.
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The hardware reference manual specifies when a pin has to be configured to
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work in bi-directional mode and when the IO direction has to be specified
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by software. Bi-directional pins are managed by the pin controller driver
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internally, while software driven IO direction has to be explicitly
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selected when multiple options are available.
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Example:
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A serial communication interface with a TX output pin and an RX input pin.
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&pinctrl {
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scif2_pins: serial2 {
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pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
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};
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};
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Pin #0 on port #3 is configured as alternate function #6.
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Pin #2 on port #3 is configured as alternate function #4.
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Example 2:
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I2c master: both SDA and SCL pins need bi-directional operations
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&pinctrl {
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i2c2_pins: i2c2 {
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pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;
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};
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};
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Pin #4 on port #1 is configured as alternate function #1.
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Pin #5 on port #1 is configured as alternate function #1.
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Both need to work in bi-directional mode, the driver manages this internally.
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Example 3:
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Multi-function timer input and output compare pins.
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Configure TIOC0A as software driven input and TIOC0B as software driven
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output.
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&pinctrl {
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tioc0_pins: tioc0 {
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tioc0_input_pins {
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pinumx = <RZA1_PINMUX(4, 0, 2)>;
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input-enable;
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};
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tioc0_output_pins {
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pinmux = <RZA1_PINMUX(4, 1, 1)>;
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output-enable;
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};
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};
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};
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&tioc0 {
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...
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pinctrl-0 = <&tioc0_pins>;
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...
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};
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Pin #0 on port #4 is configured as alternate function #2 with IO direction
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specified by software as input.
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Pin #1 on port #4 is configured as alternate function #1 with IO direction
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specified by software as output.
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- GPIO controller sub-nodes:
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Each port of the r7s72100 pin controller hardware is itself a GPIO controller.
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Different SoCs have different numbers of available pins per port, but
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generally speaking, each of them can be configured in GPIO ("port") mode
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on this hardware.
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Describe GPIO controllers using sub-nodes with the following properties.
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Required properties:
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- gpio-controller
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empty property as defined by the GPIO bindings documentation.
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- #gpio-cells
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number of cells required to identify and configure a GPIO.
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Shall be 2.
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- gpio-ranges
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Describes a GPIO controller specifying its specific pin base, the pin
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base in the global pin numbering space, and the number of controlled
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pins, as defined by the GPIO bindings documentation. Refer to
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Documentation/devicetree/bindings/gpio/gpio.txt file for a more detailed
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description.
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Example:
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A GPIO controller node, controlling 16 pins indexed from 0.
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The GPIO controller base in the global pin indexing space is pin 48, thus
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pins [0 - 15] on this controller map to pins [48 - 63] in the global pin
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indexing space.
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port3: gpio-3 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 48 16>;
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};
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A device node willing to use pins controlled by this GPIO controller, shall
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refer to it as follows:
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led1 {
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gpios = <&port3 10 GPIO_ACTIVE_LOW>;
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};
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@ -188,6 +188,17 @@ config PINCTRL_ROCKCHIP
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select GENERIC_IRQ_CHIP
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select MFD_SYSCON
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config PINCTRL_RZA1
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bool "Renesas RZ/A1 gpio and pinctrl driver"
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depends on OF
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depends on ARCH_R7S72100 || COMPILE_TEST
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select GPIOLIB
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select GENERIC_PINCTRL_GROUPS
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select GENERIC_PINMUX_FUNCTIONS
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select GENERIC_PINCONF
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help
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This selects pinctrl driver for Renesas RZ/A1 platforms.
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config PINCTRL_SINGLE
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tristate "One-register-per-pin type device tree based pinctrl driver"
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depends on OF
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@ -26,6 +26,7 @@ obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
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obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
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obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
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obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
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obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
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obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
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obj-$(CONFIG_PINCTRL_SIRF) += sirf/
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obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
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1311
drivers/pinctrl/pinctrl-rza1.c
Normal file
1311
drivers/pinctrl/pinctrl-rza1.c
Normal file
File diff suppressed because it is too large
Load Diff
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@ -1137,6 +1137,43 @@ static const unsigned int scif0_ctrl_pins[] = {
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static const unsigned int scif0_ctrl_mux[] = {
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RTS0_N_MARK, CTS0_N_MARK,
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};
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/* - SCIF1 ------------------------------------------------------------------ */
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static const unsigned int scif1_data_pins[] = {
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/* RX, TX */
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RCAR_GP_PIN(10, 19), RCAR_GP_PIN(10, 18),
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};
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static const unsigned int scif1_data_mux[] = {
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RX1_MARK, TX1_MARK,
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};
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static const unsigned int scif1_clk_pins[] = {
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/* SCK */
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RCAR_GP_PIN(10, 15),
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};
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static const unsigned int scif1_clk_mux[] = {
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SCK1_MARK,
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};
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static const unsigned int scif1_ctrl_pins[] = {
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/* RTS, CTS */
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RCAR_GP_PIN(10, 17), RCAR_GP_PIN(10, 16),
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};
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static const unsigned int scif1_ctrl_mux[] = {
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RTS1_N_MARK, CTS1_N_MARK,
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};
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/* - SCIF2 ------------------------------------------------------------------ */
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static const unsigned int scif2_data_pins[] = {
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/* RX, TX */
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RCAR_GP_PIN(10, 22), RCAR_GP_PIN(10, 21),
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};
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static const unsigned int scif2_data_mux[] = {
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RX2_MARK, TX2_MARK,
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};
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static const unsigned int scif2_clk_pins[] = {
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/* SCK */
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RCAR_GP_PIN(10, 20),
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};
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static const unsigned int scif2_clk_mux[] = {
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SCK2_MARK,
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};
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/* - SCIF3 ------------------------------------------------------------------ */
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static const unsigned int scif3_data_pins[] = {
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/* RX, TX */
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|
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@ -1680,6 +1717,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(scif0_data),
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SH_PFC_PIN_GROUP(scif0_clk),
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SH_PFC_PIN_GROUP(scif0_ctrl),
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SH_PFC_PIN_GROUP(scif1_data),
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SH_PFC_PIN_GROUP(scif1_clk),
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SH_PFC_PIN_GROUP(scif1_ctrl),
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SH_PFC_PIN_GROUP(scif2_data),
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SH_PFC_PIN_GROUP(scif2_clk),
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SH_PFC_PIN_GROUP(scif3_data),
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SH_PFC_PIN_GROUP(scif3_clk),
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SH_PFC_PIN_GROUP(sdhi0_data1),
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|
|
@ -1826,6 +1868,17 @@ static const char * const scif0_groups[] = {
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"scif0_ctrl",
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};
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static const char * const scif1_groups[] = {
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"scif1_data",
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"scif1_clk",
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"scif1_ctrl",
|
||||
};
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|
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static const char * const scif2_groups[] = {
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"scif2_data",
|
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"scif2_clk",
|
||||
};
|
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|
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static const char * const scif3_groups[] = {
|
||||
"scif3_data",
|
||||
"scif3_clk",
|
||||
|
|
@ -1924,6 +1977,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
SH_PFC_FUNCTION(msiof1),
|
||||
SH_PFC_FUNCTION(qspi),
|
||||
SH_PFC_FUNCTION(scif0),
|
||||
SH_PFC_FUNCTION(scif1),
|
||||
SH_PFC_FUNCTION(scif2),
|
||||
SH_PFC_FUNCTION(scif3),
|
||||
SH_PFC_FUNCTION(sdhi0),
|
||||
SH_PFC_FUNCTION(vin0),
|
||||
|
|
|
|||
|
|
@ -1576,6 +1576,273 @@ static const struct sh_pfc_pin pinmux_pins[] = {
|
|||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
|
||||
};
|
||||
|
||||
/* - EtherAVB --------------------------------------------------------------- */
|
||||
static const unsigned int avb_link_pins[] = {
|
||||
/* AVB_LINK */
|
||||
RCAR_GP_PIN(2, 12),
|
||||
};
|
||||
static const unsigned int avb_link_mux[] = {
|
||||
AVB_LINK_MARK,
|
||||
};
|
||||
static const unsigned int avb_magic_pins[] = {
|
||||
/* AVB_MAGIC_ */
|
||||
RCAR_GP_PIN(2, 10),
|
||||
};
|
||||
static const unsigned int avb_magic_mux[] = {
|
||||
AVB_MAGIC_MARK,
|
||||
};
|
||||
static const unsigned int avb_phy_int_pins[] = {
|
||||
/* AVB_PHY_INT */
|
||||
RCAR_GP_PIN(2, 11),
|
||||
};
|
||||
static const unsigned int avb_phy_int_mux[] = {
|
||||
AVB_PHY_INT_MARK,
|
||||
};
|
||||
static const unsigned int avb_mdc_pins[] = {
|
||||
/* AVB_MDC, AVB_MDIO */
|
||||
RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
|
||||
};
|
||||
static const unsigned int avb_mdc_mux[] = {
|
||||
AVB_MDC_MARK, AVB_MDIO_MARK,
|
||||
};
|
||||
static const unsigned int avb_mii_pins[] = {
|
||||
/*
|
||||
* AVB_TX_CTL, AVB_TXC, AVB_TD0,
|
||||
* AVB_TD1, AVB_TD2, AVB_TD3,
|
||||
* AVB_RX_CTL, AVB_RXC, AVB_RD0,
|
||||
* AVB_RD1, AVB_RD2, AVB_RD3,
|
||||
* AVB_TXCREFCLK
|
||||
*/
|
||||
PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
|
||||
PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
|
||||
PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
|
||||
PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
|
||||
PIN_NUMBER('A', 12),
|
||||
|
||||
};
|
||||
static const unsigned int avb_mii_mux[] = {
|
||||
AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
|
||||
AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
|
||||
AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
|
||||
AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
|
||||
AVB_TXCREFCLK_MARK,
|
||||
};
|
||||
static const unsigned int avb_avtp_pps_pins[] = {
|
||||
/* AVB_AVTP_PPS */
|
||||
RCAR_GP_PIN(2, 6),
|
||||
};
|
||||
static const unsigned int avb_avtp_pps_mux[] = {
|
||||
AVB_AVTP_PPS_MARK,
|
||||
};
|
||||
static const unsigned int avb_avtp_match_a_pins[] = {
|
||||
/* AVB_AVTP_MATCH_A */
|
||||
RCAR_GP_PIN(2, 13),
|
||||
};
|
||||
static const unsigned int avb_avtp_match_a_mux[] = {
|
||||
AVB_AVTP_MATCH_A_MARK,
|
||||
};
|
||||
static const unsigned int avb_avtp_capture_a_pins[] = {
|
||||
/* AVB_AVTP_CAPTURE_A */
|
||||
RCAR_GP_PIN(2, 14),
|
||||
};
|
||||
static const unsigned int avb_avtp_capture_a_mux[] = {
|
||||
AVB_AVTP_CAPTURE_A_MARK,
|
||||
};
|
||||
static const unsigned int avb_avtp_match_b_pins[] = {
|
||||
/* AVB_AVTP_MATCH_B */
|
||||
RCAR_GP_PIN(1, 8),
|
||||
};
|
||||
static const unsigned int avb_avtp_match_b_mux[] = {
|
||||
AVB_AVTP_MATCH_B_MARK,
|
||||
};
|
||||
static const unsigned int avb_avtp_capture_b_pins[] = {
|
||||
/* AVB_AVTP_CAPTURE_B */
|
||||
RCAR_GP_PIN(1, 11),
|
||||
};
|
||||
static const unsigned int avb_avtp_capture_b_mux[] = {
|
||||
AVB_AVTP_CAPTURE_B_MARK,
|
||||
};
|
||||
|
||||
/* - DU --------------------------------------------------------------------- */
|
||||
static const unsigned int du_rgb666_pins[] = {
|
||||
/* R[7:2], G[7:2], B[7:2] */
|
||||
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
|
||||
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
|
||||
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
|
||||
};
|
||||
static const unsigned int du_rgb666_mux[] = {
|
||||
DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
|
||||
DU_DR3_MARK, DU_DR2_MARK,
|
||||
DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
|
||||
DU_DG3_MARK, DU_DG2_MARK,
|
||||
DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
|
||||
DU_DB3_MARK, DU_DB2_MARK,
|
||||
};
|
||||
static const unsigned int du_rgb888_pins[] = {
|
||||
/* R[7:0], G[7:0], B[7:0] */
|
||||
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
|
||||
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
|
||||
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
|
||||
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
|
||||
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
|
||||
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
|
||||
};
|
||||
static const unsigned int du_rgb888_mux[] = {
|
||||
DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
|
||||
DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
|
||||
DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
|
||||
DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
|
||||
DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
|
||||
DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
|
||||
};
|
||||
static const unsigned int du_clk_out_0_pins[] = {
|
||||
/* CLKOUT */
|
||||
RCAR_GP_PIN(1, 27),
|
||||
};
|
||||
static const unsigned int du_clk_out_0_mux[] = {
|
||||
DU_DOTCLKOUT0_MARK
|
||||
};
|
||||
static const unsigned int du_clk_out_1_pins[] = {
|
||||
/* CLKOUT */
|
||||
RCAR_GP_PIN(2, 3),
|
||||
};
|
||||
static const unsigned int du_clk_out_1_mux[] = {
|
||||
DU_DOTCLKOUT1_MARK
|
||||
};
|
||||
static const unsigned int du_sync_pins[] = {
|
||||
/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
|
||||
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
|
||||
};
|
||||
static const unsigned int du_sync_mux[] = {
|
||||
DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
|
||||
};
|
||||
static const unsigned int du_oddf_pins[] = {
|
||||
/* EXDISP/EXODDF/EXCDE */
|
||||
RCAR_GP_PIN(2, 2),
|
||||
};
|
||||
static const unsigned int du_oddf_mux[] = {
|
||||
DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
|
||||
};
|
||||
static const unsigned int du_cde_pins[] = {
|
||||
/* CDE */
|
||||
RCAR_GP_PIN(2, 0),
|
||||
};
|
||||
static const unsigned int du_cde_mux[] = {
|
||||
DU_CDE_MARK,
|
||||
};
|
||||
static const unsigned int du_disp_pins[] = {
|
||||
/* DISP */
|
||||
RCAR_GP_PIN(2, 1),
|
||||
};
|
||||
static const unsigned int du_disp_mux[] = {
|
||||
DU_DISP_MARK,
|
||||
};
|
||||
|
||||
/* - PWM0 --------------------------------------------------------------------*/
|
||||
static const unsigned int pwm0_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 6),
|
||||
};
|
||||
static const unsigned int pwm0_mux[] = {
|
||||
PWM0_MARK,
|
||||
};
|
||||
/* - PWM1 --------------------------------------------------------------------*/
|
||||
static const unsigned int pwm1_a_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 7),
|
||||
};
|
||||
static const unsigned int pwm1_a_mux[] = {
|
||||
PWM1_A_MARK,
|
||||
};
|
||||
static const unsigned int pwm1_b_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(1, 8),
|
||||
};
|
||||
static const unsigned int pwm1_b_mux[] = {
|
||||
PWM1_B_MARK,
|
||||
};
|
||||
/* - PWM2 --------------------------------------------------------------------*/
|
||||
static const unsigned int pwm2_a_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 8),
|
||||
};
|
||||
static const unsigned int pwm2_a_mux[] = {
|
||||
PWM2_A_MARK,
|
||||
};
|
||||
static const unsigned int pwm2_b_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(1, 11),
|
||||
};
|
||||
static const unsigned int pwm2_b_mux[] = {
|
||||
PWM2_B_MARK,
|
||||
};
|
||||
/* - PWM3 --------------------------------------------------------------------*/
|
||||
static const unsigned int pwm3_a_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(1, 0),
|
||||
};
|
||||
static const unsigned int pwm3_a_mux[] = {
|
||||
PWM3_A_MARK,
|
||||
};
|
||||
static const unsigned int pwm3_b_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 2),
|
||||
};
|
||||
static const unsigned int pwm3_b_mux[] = {
|
||||
PWM3_B_MARK,
|
||||
};
|
||||
/* - PWM4 --------------------------------------------------------------------*/
|
||||
static const unsigned int pwm4_a_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(1, 1),
|
||||
};
|
||||
static const unsigned int pwm4_a_mux[] = {
|
||||
PWM4_A_MARK,
|
||||
};
|
||||
static const unsigned int pwm4_b_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 3),
|
||||
};
|
||||
static const unsigned int pwm4_b_mux[] = {
|
||||
PWM4_B_MARK,
|
||||
};
|
||||
/* - PWM5 --------------------------------------------------------------------*/
|
||||
static const unsigned int pwm5_a_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(1, 2),
|
||||
};
|
||||
static const unsigned int pwm5_a_mux[] = {
|
||||
PWM5_A_MARK,
|
||||
};
|
||||
static const unsigned int pwm5_b_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 4),
|
||||
};
|
||||
static const unsigned int pwm5_b_mux[] = {
|
||||
PWM5_B_MARK,
|
||||
};
|
||||
/* - PWM6 --------------------------------------------------------------------*/
|
||||
static const unsigned int pwm6_a_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(1, 3),
|
||||
};
|
||||
static const unsigned int pwm6_a_mux[] = {
|
||||
PWM6_A_MARK,
|
||||
};
|
||||
static const unsigned int pwm6_b_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 5),
|
||||
};
|
||||
static const unsigned int pwm6_b_mux[] = {
|
||||
PWM6_B_MARK,
|
||||
};
|
||||
|
||||
/* - SCIF0 ------------------------------------------------------------------ */
|
||||
static const unsigned int scif0_data_pins[] = {
|
||||
/* RX, TX */
|
||||
|
|
@ -1790,6 +2057,37 @@ static const unsigned int scif_clk_b_mux[] = {
|
|||
};
|
||||
|
||||
static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(avb_link),
|
||||
SH_PFC_PIN_GROUP(avb_magic),
|
||||
SH_PFC_PIN_GROUP(avb_phy_int),
|
||||
SH_PFC_PIN_GROUP(avb_mdc),
|
||||
SH_PFC_PIN_GROUP(avb_mii),
|
||||
SH_PFC_PIN_GROUP(avb_avtp_pps),
|
||||
SH_PFC_PIN_GROUP(avb_avtp_match_a),
|
||||
SH_PFC_PIN_GROUP(avb_avtp_capture_a),
|
||||
SH_PFC_PIN_GROUP(avb_avtp_match_b),
|
||||
SH_PFC_PIN_GROUP(avb_avtp_capture_b),
|
||||
SH_PFC_PIN_GROUP(du_rgb666),
|
||||
SH_PFC_PIN_GROUP(du_rgb888),
|
||||
SH_PFC_PIN_GROUP(du_clk_out_0),
|
||||
SH_PFC_PIN_GROUP(du_clk_out_1),
|
||||
SH_PFC_PIN_GROUP(du_sync),
|
||||
SH_PFC_PIN_GROUP(du_oddf),
|
||||
SH_PFC_PIN_GROUP(du_cde),
|
||||
SH_PFC_PIN_GROUP(du_disp),
|
||||
SH_PFC_PIN_GROUP(pwm0),
|
||||
SH_PFC_PIN_GROUP(pwm1_a),
|
||||
SH_PFC_PIN_GROUP(pwm1_b),
|
||||
SH_PFC_PIN_GROUP(pwm2_a),
|
||||
SH_PFC_PIN_GROUP(pwm2_b),
|
||||
SH_PFC_PIN_GROUP(pwm3_a),
|
||||
SH_PFC_PIN_GROUP(pwm3_b),
|
||||
SH_PFC_PIN_GROUP(pwm4_a),
|
||||
SH_PFC_PIN_GROUP(pwm4_b),
|
||||
SH_PFC_PIN_GROUP(pwm5_a),
|
||||
SH_PFC_PIN_GROUP(pwm5_b),
|
||||
SH_PFC_PIN_GROUP(pwm6_a),
|
||||
SH_PFC_PIN_GROUP(pwm6_b),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
SH_PFC_PIN_GROUP(scif0_clk),
|
||||
SH_PFC_PIN_GROUP(scif0_ctrl),
|
||||
|
|
@ -1821,6 +2119,64 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(scif_clk_b),
|
||||
};
|
||||
|
||||
static const char * const avb_groups[] = {
|
||||
"avb_link",
|
||||
"avb_magic",
|
||||
"avb_phy_int",
|
||||
"avb_mdc",
|
||||
"avb_mii",
|
||||
"avb_avtp_pps",
|
||||
"avb_avtp_match_a",
|
||||
"avb_avtp_capture_a",
|
||||
"avb_avtp_match_b",
|
||||
"avb_avtp_capture_b",
|
||||
};
|
||||
|
||||
static const char * const du_groups[] = {
|
||||
"du_rgb666",
|
||||
"du_rgb888",
|
||||
"du_clk_out_0",
|
||||
"du_clk_out_1",
|
||||
"du_sync",
|
||||
"du_oddf",
|
||||
"du_cde",
|
||||
"du_disp",
|
||||
};
|
||||
|
||||
static const char * const pwm0_groups[] = {
|
||||
"pwm0",
|
||||
};
|
||||
|
||||
static const char * const pwm1_groups[] = {
|
||||
"pwm1_a",
|
||||
"pwm1_b",
|
||||
};
|
||||
|
||||
static const char * const pwm2_groups[] = {
|
||||
"pwm2_a",
|
||||
"pwm2_b",
|
||||
};
|
||||
|
||||
static const char * const pwm3_groups[] = {
|
||||
"pwm3_a",
|
||||
"pwm3_b",
|
||||
};
|
||||
|
||||
static const char * const pwm4_groups[] = {
|
||||
"pwm4_a",
|
||||
"pwm4_b",
|
||||
};
|
||||
|
||||
static const char * const pwm5_groups[] = {
|
||||
"pwm5_a",
|
||||
"pwm5_b",
|
||||
};
|
||||
|
||||
static const char * const pwm6_groups[] = {
|
||||
"pwm6_a",
|
||||
"pwm6_b",
|
||||
};
|
||||
|
||||
static const char * const scif0_groups[] = {
|
||||
"scif0_data",
|
||||
"scif0_clk",
|
||||
|
|
@ -1872,6 +2228,15 @@ static const char * const scif_clk_groups[] = {
|
|||
};
|
||||
|
||||
static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(avb),
|
||||
SH_PFC_FUNCTION(du),
|
||||
SH_PFC_FUNCTION(pwm0),
|
||||
SH_PFC_FUNCTION(pwm1),
|
||||
SH_PFC_FUNCTION(pwm2),
|
||||
SH_PFC_FUNCTION(pwm3),
|
||||
SH_PFC_FUNCTION(pwm4),
|
||||
SH_PFC_FUNCTION(pwm5),
|
||||
SH_PFC_FUNCTION(pwm6),
|
||||
SH_PFC_FUNCTION(scif0),
|
||||
SH_PFC_FUNCTION(scif1),
|
||||
SH_PFC_FUNCTION(scif2),
|
||||
|
|
|
|||
16
include/dt-bindings/pinctrl/r7s72100-pinctrl.h
Normal file
16
include/dt-bindings/pinctrl/r7s72100-pinctrl.h
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* Defines macros and constants for Renesas RZ/A1 pin controller pin
|
||||
* muxing functions.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
|
||||
#define __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
|
||||
|
||||
#define RZA1_PINS_PER_PORT 16
|
||||
|
||||
/*
|
||||
* Create the pin index from its bank and position numbers and store in
|
||||
* the upper 16 bits the alternate function identifier
|
||||
*/
|
||||
#define RZA1_PINMUX(b, p, f) ((b) * RZA1_PINS_PER_PORT + (p) | (f << 16))
|
||||
|
||||
#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H */
|
||||
Loading…
Reference in New Issue
Block a user