forked from luck/tmp_suning_uos_patched
bcma: add an extra pcie core struct
The BCM4706 has two PCIe host controller on the bcma bus. For PCIe client mode it is assumed that there is only one PCIe controller so the PCIe driver, like b43 and brcmsmac are accessing the first PCIe controller when they want to issue a operation on the host controller. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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017c4c3bde
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@ -452,6 +452,8 @@ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
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pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
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pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
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BCMA_SOC_PCI_MEM_SZ - 1;
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pc_host->io_resource.start = 0x100;
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pc_host->io_resource.end = 0x47F;
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pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
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pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
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tmp | BCMA_SOC_PCI_MEM);
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@ -459,6 +461,8 @@ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
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pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
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pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
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BCMA_SOC_PCI_MEM_SZ - 1;
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pc_host->io_resource.start = 0x480;
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pc_host->io_resource.end = 0x7FF;
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pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
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pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
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pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
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@ -81,6 +81,18 @@ struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
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}
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EXPORT_SYMBOL_GPL(bcma_find_core);
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static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
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u8 unit)
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{
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struct bcma_device *core;
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list_for_each_entry(core, &bus->cores, list) {
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if (core->id.id == coreid && core->core_unit == unit)
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return core;
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}
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return NULL;
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}
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static void bcma_release_core_dev(struct device *dev)
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{
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struct bcma_device *core = container_of(dev, struct bcma_device, dev);
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@ -211,10 +223,17 @@ int __devinit bcma_bus_register(struct bcma_bus *bus)
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}
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/* Init PCIE core */
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core = bcma_find_core(bus, BCMA_CORE_PCIE);
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core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
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if (core) {
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bus->drv_pci.core = core;
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bcma_core_pci_init(&bus->drv_pci);
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bus->drv_pci[0].core = core;
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bcma_core_pci_init(&bus->drv_pci[0]);
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}
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/* Init PCIE core */
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core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
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if (core) {
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bus->drv_pci[1].core = core;
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bcma_core_pci_init(&bus->drv_pci[1]);
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}
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/* Init GBIT MAC COMMON core */
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@ -4652,7 +4652,7 @@ static int b43_wireless_core_init(struct b43_wldev *dev)
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switch (dev->dev->bus_type) {
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#ifdef CONFIG_B43_BCMA
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case B43_BUS_BCMA:
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bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
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bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
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dev->dev->bdev, true);
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break;
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#endif
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@ -692,7 +692,7 @@ void ai_pci_up(struct si_pub *sih)
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sii = container_of(sih, struct si_info, pub);
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if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
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bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
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bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
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}
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/* Unconfigure and/or apply various WARs when going down */
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@ -703,7 +703,7 @@ void ai_pci_down(struct si_pub *sih)
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sii = container_of(sih, struct si_info, pub);
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if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
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bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
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bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
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}
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/* Enable BT-COEX & Ex-PA for 4313 */
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@ -5077,7 +5077,7 @@ static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
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* Configure pci/pcmcia here instead of in brcms_c_attach()
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* to allow mfg hotswap: down, hotswap (chip power cycle), up.
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*/
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bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
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bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
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true);
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/*
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@ -251,7 +251,7 @@ struct bcma_bus {
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u8 num;
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struct bcma_drv_cc drv_cc;
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struct bcma_drv_pci drv_pci;
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struct bcma_drv_pci drv_pci[2];
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struct bcma_drv_mips drv_mips;
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struct bcma_drv_gmac_cmn drv_gmac_cmn;
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