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mips/atomic: Fix cmpxchg64 barriers

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There were no memory barriers on the 32bit implementation of
cmpxchg64(). Fix this.

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
This commit is contained in:
Peter Zijlstra 2019-06-13 15:43:18 +02:00 committed by Paul Burton
parent 00f3e68951
commit dfc8d8de85
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1 changed files with 5 additions and 2 deletions
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7
arch/mips/include/asm/cmpxchg.h
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@ -290,10 +290,13 @@ static inline unsigned long __cmpxchg64(volatile void *ptr,
* will cause a build error unless cpu_has_64bits is a \
* compile-time constant 1. \
*/ \
if (cpu_has_64bits && kernel_uses_llsc) \
if (cpu_has_64bits && kernel_uses_llsc) { \
smp_mb__before_llsc(); \
__res = __cmpxchg64((ptr), __old, __new); \
else \
smp_llsc_mb(); \
} else { \
__res = __cmpxchg64_unsupported(); \
} \
\
__res; \
})