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MIPS: Add defs & probing of BadInstr[P] registers

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The optional CP0_BadInstr and CP0_BadInstrP registers are written with
the encoding of the instruction that caused a synchronous exception to
occur, and the prior branch instruction if in a delay slot.

These will be useful for instruction emulation in KVM, and especially
for VZ support where reading guest virtual memory is a bit more awkward.

Add CPU option numbers and cpu_has_* definitions to indicate the
presence of each registers, and add code to probe for them using bits in
the CP0_Config3 register.

[ralf@linux-mips.org: resolve merge conflict.]

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13224/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
James Hogan 2016-05-11 13:50:51 +01:00 committed by Ralf Baechle
parent 37fb60f8e3
commit e06a1548f3
4 changed files with 17 additions and 0 deletions
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8
arch/mips/include/asm/cpu-features.h
View File

@ -442,4 +442,12 @@
# define cpu_has_ebase_wg (cpu_data[0].options & MIPS_CPU_EBASE_WG)
#endif
#ifndef cpu_has_badinstr
# define cpu_has_badinstr (cpu_data[0].options & MIPS_CPU_BADINSTR)
#endif
#ifndef cpu_has_badinstrp
# define cpu_has_badinstrp (cpu_data[0].options & MIPS_CPU_BADINSTRP)
#endif
#endif /* __ASM_CPU_FEATURES_H */

2
arch/mips/include/asm/cpu.h
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@ -405,6 +405,8 @@ enum cpu_type_enum {
#define MIPS_CPU_LDPTE MBIT_ULL(41) /* CPU has ldpte/lddir instructions */
#define MIPS_CPU_MVH MBIT_ULL(42) /* CPU supports MFHC0/MTHC0 */
#define MIPS_CPU_EBASE_WG MBIT_ULL(43) /* CPU has EBase.WG */
#define MIPS_CPU_BADINSTR MBIT_ULL(44) /* CPU has BadInstr register */
#define MIPS_CPU_BADINSTRP MBIT_ULL(45) /* CPU has BadInstrP register */
/*
* CPU ASE encodings

3
arch/mips/include/asm/mipsregs.h
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@ -1248,6 +1248,9 @@ do { \
#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
#define read_c0_badinstr() __read_32bit_c0_register($8, 1)
#define read_c0_badinstrp() __read_32bit_c0_register($8, 2)
#define read_c0_count() __read_32bit_c0_register($9, 0)
#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)

4
arch/mips/kernel/cpu-probe.c
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@ -714,6 +714,10 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
c->ases |= MIPS_ASE_VZ;
if (config3 & MIPS_CONF3_SC)
c->options |= MIPS_CPU_SEGMENTS;
if (config3 & MIPS_CONF3_BI)
c->options |= MIPS_CPU_BADINSTR;
if (config3 & MIPS_CONF3_BP)
c->options |= MIPS_CPU_BADINSTRP;
if (config3 & MIPS_CONF3_MSA)
c->ases |= MIPS_ASE_MSA;
if (config3 & MIPS_CONF3_PW) {