forked from luck/tmp_suning_uos_patched
sh: intc - add support for SH7760
This patch converts the cpu specific interrupt setup code for sh7760 from ipr + intc2 to intc. New vectors are also added to match the information provided by the datasheet. Vectors for IRQ4-IRQ7 are enabled by default. Use plat_irq_setup_pins() if pins IRL0-3 should be used in IRLM mode. The patch also adds the SIM block to the serial port platform data. Version two of this patch fixes MMCIF problems reported by Manuel Lauss. Signed-off-by: Magnus Damm <damm@igel.co.jp> Acked-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
a0e23267d4
commit
e29bfbc443
@ -12,6 +12,136 @@
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#include <linux/serial.h>
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#include <asm/sci.h>
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRL0, IRL1, IRL2, IRL3,
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HUDI, GPIOI,
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DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
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DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
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DMAC_DMAE,
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IRQ4, IRQ5, IRQ6, IRQ7,
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HCAN20, HCAN21,
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SSI0, SSI1,
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HAC0, HAC1,
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I2C0, I2C1,
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USB, LCDC,
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DMABRG0, DMABRG1, DMABRG2,
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SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
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SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
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SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
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SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
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HSPI,
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MMCIF0, MMCIF1, MMCIF2, MMCIF3,
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MFI, ADC, CMT,
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TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
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WDT,
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REF_RCMI, REF_ROVI,
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/* interrupt groups */
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DMAC, DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF, TMU2, REF,
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};
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static struct intc_vect vectors[] = {
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INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
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INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
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INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
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INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
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INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
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INTC_VECT(DMAC_DMAE, 0x6c0),
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INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
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INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
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INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
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INTC_VECT(SSI0, 0x940), INTC_VECT(SSI1, 0x960),
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INTC_VECT(HAC0, 0x980), INTC_VECT(HAC1, 0x9a0),
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INTC_VECT(I2C0, 0x9c0), INTC_VECT(I2C1, 0x9e0),
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INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),
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INTC_VECT(DMABRG0, 0xa80), INTC_VECT(DMABRG1, 0xaa0),
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INTC_VECT(DMABRG2, 0xac0),
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INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
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INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
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INTC_VECT(SCIF1_ERI, 0xb00), INTC_VECT(SCIF1_RXI, 0xb20),
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INTC_VECT(SCIF1_BRI, 0xb40), INTC_VECT(SCIF1_TXI, 0xb60),
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INTC_VECT(SCIF2_ERI, 0xb80), INTC_VECT(SCIF2_RXI, 0xba0),
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INTC_VECT(SCIF2_BRI, 0xbc0), INTC_VECT(SCIF2_TXI, 0xbe0),
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INTC_VECT(SIM_ERI, 0xc00), INTC_VECT(SIM_RXI, 0xc20),
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INTC_VECT(SIM_TXI, 0xc40), INTC_VECT(SIM_TEI, 0xc60),
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INTC_VECT(HSPI, 0xc80),
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INTC_VECT(MMCIF0, 0xd00), INTC_VECT(MMCIF1, 0xd20),
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INTC_VECT(MMCIF2, 0xd40), INTC_VECT(MMCIF3, 0xd60),
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INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */
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INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0),
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INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
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INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
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INTC_VECT(WDT, 0x560),
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INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
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};
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static struct intc_group groups[] = {
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INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
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DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
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DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
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INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2),
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INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
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INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
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INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
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INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
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INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3),
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INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
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INTC_GROUP(REF, REF_RCMI, REF_ROVI),
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};
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static struct intc_prio priorities[] = {
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INTC_PRIO(SCIF0, 3),
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INTC_PRIO(SCIF1, 3),
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INTC_PRIO(SCIF2, 3),
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INTC_PRIO(SIM, 3),
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INTC_PRIO(DMAC, 7),
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INTC_PRIO(DMABRG, 13),
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};
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static struct intc_mask_reg mask_registers[] = {
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{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
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{ IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21,
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SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
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0, DMABRG0, DMABRG1, DMABRG2,
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SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
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SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
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SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, } },
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{ 0xfe080044, 0xfe080064, 32, /* INTMSK04 / INTMSKCLR04 */
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{ 0, 0, 0, 0, 0, 0, 0, 0,
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SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
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HSPI, MMCIF0, MMCIF1, MMCIF2,
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MMCIF3, 0, 0, 0, 0, 0, 0, 0,
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0, MFI, 0, 0, 0, 0, ADC, CMT, } },
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};
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static struct intc_prio_reg prio_registers[] = {
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{ 0xffd00004, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
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{ 0xffd00008, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
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{ 0xffd0000c, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } },
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{ 0xffd00010, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
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{ 0xfe080000, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
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{ 0xfe080004, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1,
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HAC0, HAC1, I2C0, I2C1 } },
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{ 0xfe080008, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,
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SCIF1, SCIF2, SIM, HSPI } },
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{ 0xfe08000c, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0,
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MFI, 0, ADC, CMT } },
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};
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static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups,
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priorities, mask_registers, prio_registers, NULL);
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static struct intc_vect vectors_irq[] = {
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INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
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INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
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};
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static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
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priorities, mask_registers, prio_registers, NULL);
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static struct plat_sci_port sci_platform_data[] = {
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{
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.mapbase = 0xfe600000,
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@ -28,6 +158,11 @@ static struct plat_sci_port sci_platform_data[] = {
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 76, 77, 79, 78 },
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}, {
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.mapbase = 0xfe480000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCI,
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.irqs = { 80, 81, 82, 0 },
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}, {
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.flags = 0,
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}
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@ -52,114 +187,18 @@ static int __init sh7760_devices_setup(void)
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}
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__initcall(sh7760_devices_setup);
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static struct intc2_data intc2_irq_table[] = {
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{48, 0, 28, 0, 31, 3}, /* IRQ 4 */
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{49, 0, 24, 0, 30, 3}, /* IRQ 3 */
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{50, 0, 20, 0, 29, 3}, /* IRQ 2 */
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{51, 0, 16, 0, 28, 3}, /* IRQ 1 */
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{56, 4, 28, 0, 25, 3}, /* HCAN2_CHAN0 */
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{57, 4, 24, 0, 24, 3}, /* HCAN2_CHAN1 */
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{58, 4, 20, 0, 23, 3}, /* I2S_CHAN0 */
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{59, 4, 16, 0, 22, 3}, /* I2S_CHAN1 */
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{60, 4, 12, 0, 21, 3}, /* AC97_CHAN0 */
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{61, 4, 8, 0, 20, 3}, /* AC97_CHAN1 */
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{62, 4, 4, 0, 19, 3}, /* I2C_CHAN0 */
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{63, 4, 0, 0, 18, 3}, /* I2C_CHAN1 */
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{52, 8, 16, 0, 11, 3}, /* SCIF0_ERI_IRQ */
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{53, 8, 16, 0, 10, 3}, /* SCIF0_RXI_IRQ */
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{54, 8, 16, 0, 9, 3}, /* SCIF0_BRI_IRQ */
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{55, 8, 16, 0, 8, 3}, /* SCIF0_TXI_IRQ */
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{64, 8, 28, 0, 17, 3}, /* USBHI_IRQ */
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{65, 8, 24, 0, 16, 3}, /* LCDC */
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{68, 8, 20, 0, 14, 13}, /* DMABRGI0_IRQ */
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{69, 8, 20, 0, 13, 13}, /* DMABRGI1_IRQ */
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{70, 8, 20, 0, 12, 13}, /* DMABRGI2_IRQ */
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{72, 8, 12, 0, 7, 3}, /* SCIF1_ERI_IRQ */
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{73, 8, 12, 0, 6, 3}, /* SCIF1_RXI_IRQ */
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{74, 8, 12, 0, 5, 3}, /* SCIF1_BRI_IRQ */
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{75, 8, 12, 0, 4, 3}, /* SCIF1_TXI_IRQ */
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{76, 8, 8, 0, 3, 3}, /* SCIF2_ERI_IRQ */
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{77, 8, 8, 0, 2, 3}, /* SCIF2_RXI_IRQ */
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{78, 8, 8, 0, 1, 3}, /* SCIF2_BRI_IRQ */
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{79, 8, 8, 0, 0, 3}, /* SCIF2_TXI_IRQ */
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{80, 8, 4, 4, 23, 3}, /* SIM_ERI */
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{81, 8, 4, 4, 22, 3}, /* SIM_RXI */
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{82, 8, 4, 4, 21, 3}, /* SIM_TXI */
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{83, 8, 4, 4, 20, 3}, /* SIM_TEI */
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{84, 8, 0, 4, 19, 3}, /* HSPII */
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{88, 12, 20, 4, 18, 3}, /* MMCI0 */
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{89, 12, 20, 4, 17, 3}, /* MMCI1 */
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{90, 12, 20, 4, 16, 3}, /* MMCI2 */
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{91, 12, 20, 4, 15, 3}, /* MMCI3 */
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{92, 12, 12, 4, 6, 3}, /* MFI */
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{108,12, 4, 4, 1, 3}, /* ADC */
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{109,12, 0, 4, 0, 3}, /* CMTI */
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};
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static struct intc2_desc intc2_irq_desc __read_mostly = {
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.prio_base = 0xfe080000,
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.msk_base = 0xfe080040,
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.mskclr_base = 0xfe080060,
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.intc2_data = intc2_irq_table,
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.nr_irqs = ARRAY_SIZE(intc2_irq_table),
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.chip = {
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.name = "INTC2-sh7760",
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},
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};
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static struct ipr_data ipr_irq_table[] = {
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/* IRQ, IPR-idx, shift, priority */
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{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
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{ 17, 0, 8, 2 }, /* TMU1 TUNI */
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{ 18, 0, 4, 2 }, /* TMU2 TUNI */
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{ 19, 0, 4, 2 }, /* TMU2 TIPCI */
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{ 27, 1, 12, 2 }, /* WDT ITI */
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{ 28, 1, 8, 2 }, /* REF RCMI */
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{ 29, 1, 8, 2 }, /* REF ROVI */
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{ 32, 2, 0, 7 }, /* HUDI */
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{ 33, 2, 12, 7 }, /* GPIOI */
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{ 34, 2, 8, 7 }, /* DMAC DMTE0 */
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{ 35, 2, 8, 7 }, /* DMAC DMTE1 */
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{ 36, 2, 8, 7 }, /* DMAC DMTE2 */
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{ 37, 2, 8, 7 }, /* DMAC DMTE3 */
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{ 38, 2, 8, 7 }, /* DMAC DMAE */
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{ 44, 2, 8, 7 }, /* DMAC DMTE4 */
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{ 45, 2, 8, 7 }, /* DMAC DMTE5 */
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{ 46, 2, 8, 7 }, /* DMAC DMTE6 */
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{ 47, 2, 8, 7 }, /* DMAC DMTE7 */
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/* these here are only valid if INTC_ICR bit 7 is set to 1!
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* XXX: maybe CONFIG_SH_IRLMODE symbol? SH7751 could use it too */
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#if 0
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{ 2, 3, 12, 3 }, /* IRL0 */
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{ 5, 3, 8, 3 }, /* IRL1 */
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{ 8, 3, 4, 3 }, /* IRL2 */
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{ 11, 3, 0, 3 }, /* IRL3 */
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#endif
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};
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static unsigned long ipr_offsets[] = {
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0xffd00004UL, /* 0: IPRA */
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0xffd00008UL, /* 1: IPRB */
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0xffd0000cUL, /* 2: IPRC */
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0xffd00010UL, /* 3: IPRD */
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};
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static struct ipr_desc ipr_irq_desc = {
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.ipr_offsets = ipr_offsets,
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.nr_offsets = ARRAY_SIZE(ipr_offsets),
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.ipr_data = ipr_irq_table,
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.nr_irqs = ARRAY_SIZE(ipr_irq_table),
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.chip = {
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.name = "IPR-sh7760",
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},
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};
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void __init plat_irq_setup_pins(int mode)
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{
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switch (mode) {
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case IRQ_MODE_IRQ:
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register_intc_controller(&intc_desc_irq);
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break;
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default:
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BUG();
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}
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}
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void __init plat_irq_setup(void)
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{
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register_intc2_controller(&intc2_irq_desc);
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register_ipr_controller(&ipr_irq_desc);
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register_intc_controller(&intc_desc);
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}
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@ -155,8 +155,7 @@ config CPU_SUBTYPE_SH7751R
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config CPU_SUBTYPE_SH7760
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bool "Support SH7760 processor"
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select CPU_SH4
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select CPU_HAS_INTC2_IRQ
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select CPU_HAS_IPR_IRQ
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select CPU_HAS_INTC_IRQ
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config CPU_SUBTYPE_SH4_202
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bool "Support SH4-202 processor"
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