forked from luck/tmp_suning_uos_patched
agp/intel: Sandybridge doesn't require GMCH enabling
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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c584fe47e4
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e380f60b22
@ -922,10 +922,11 @@ static void i830_write_entry(dma_addr_t addr, unsigned int entry,
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writel(addr | pte_flags, intel_private.gtt + entry);
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}
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static void intel_enable_gtt(void)
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static bool intel_enable_gtt(void)
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{
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u32 gma_addr;
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u16 gmch_ctrl;
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u8 __iomem *reg;
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if (INTEL_GTT_GEN == 2)
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pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
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@ -936,13 +937,34 @@ static void intel_enable_gtt(void)
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intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
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pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl);
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gmch_ctrl |= I830_GMCH_ENABLED;
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pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl);
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if (INTEL_GTT_GEN >= 6)
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return true;
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writel(intel_private.PGETBL_save|I810_PGETBL_ENABLED,
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intel_private.registers+I810_PGETBL_CTL);
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readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
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pci_read_config_word(intel_private.bridge_dev,
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I830_GMCH_CTRL, &gmch_ctrl);
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gmch_ctrl |= I830_GMCH_ENABLED;
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pci_write_config_word(intel_private.bridge_dev,
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I830_GMCH_CTRL, gmch_ctrl);
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pci_read_config_word(intel_private.bridge_dev,
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I830_GMCH_CTRL, &gmch_ctrl);
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if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
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dev_err(&intel_private.pcidev->dev,
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"failed to enable the GTT: GMCH_CTRL=%x\n",
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gmch_ctrl);
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return false;
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}
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reg = intel_private.registers+I810_PGETBL_CTL;
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writel(intel_private.PGETBL_save|I810_PGETBL_ENABLED, reg);
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if ((readl(reg) & I810_PGETBL_ENABLED) == 0) {
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dev_err(&intel_private.pcidev->dev,
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"failed to enable the GTT: PGETBL=%x [expected %x|1]\n",
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readl(reg), intel_private.PGETBL_save);
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return false;
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}
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return true;
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}
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static int i830_setup(void)
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@ -981,7 +1003,8 @@ static int intel_fake_agp_configure(void)
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{
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int i;
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intel_enable_gtt();
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if (!intel_enable_gtt())
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return -EIO;
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agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
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