AcoSail/kernel_optimize_test
8
0
Fork 0
forked from luck/tmp_suning_uos_patched
Code Pull Requests Activity

ARM: socfpga: add bindings document for fpga bridge drivers

Browse Source 
Add bindings documentation for Altera SOCFPGA bridges:
 * fpga2sdram
 * fpga2hps
 * hps2fpga
 * lwhps2fpga

Signed-off-by: Alan Tull <atull@opensource.altera.com>
Signed-off-by: Matthew Gerlach <mgerlach@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Alan Tull 2016-07-12 14:36:41 -05:00 committed by Rob Herring
parent e5269794d2
commit e3d19244c8
2 changed files with 55 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt Normal file
View File

@ -0,0 +1,16 @@
Altera FPGA To SDRAM Bridge Driver
Required properties:
- compatible : Should contain "altr,socfpga-fpga2sdram-bridge"
Optional properties:
- bridge-enable : 0 if driver should disable bridge at startup
1 if driver should enable bridge at startup
Default is to leave bridge in current state.
Example:
fpga_bridge3: fpga-bridge@ffc25080 {
compatible = "altr,socfpga-fpga2sdram-bridge";
reg = <0xffc25080 0x4>;
bridge-enable = <0>;
};

39
Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt Normal file
View File

@ -0,0 +1,39 @@
Altera FPGA/HPS Bridge Driver
Required properties:
- regs : base address and size for AXI bridge module
- compatible : Should contain one of:
"altr,socfpga-lwhps2fpga-bridge",
"altr,socfpga-hps2fpga-bridge", or
"altr,socfpga-fpga2hps-bridge"
- resets : Phandle and reset specifier for this bridge's reset
- clocks : Clocks used by this module.
Optional properties:
- bridge-enable : 0 if driver should disable bridge at startup.
1 if driver should enable bridge at startup.
Default is to leave bridge in its current state.
Example:
fpga_bridge0: fpga-bridge@ff400000 {
compatible = "altr,socfpga-lwhps2fpga-bridge";
reg = <0xff400000 0x100000>;
resets = <&rst LWHPS2FPGA_RESET>;
clocks = <&l4_main_clk>;
bridge-enable = <0>;
};
fpga_bridge1: fpga-bridge@ff500000 {
compatible = "altr,socfpga-hps2fpga-bridge";
reg = <0xff500000 0x10000>;
resets = <&rst HPS2FPGA_RESET>;
clocks = <&l4_main_clk>;
bridge-enable = <1>;
};
fpga_bridge2: fpga-bridge@ff600000 {
compatible = "altr,socfpga-fpga2hps-bridge";
reg = <0xff600000 0x100000>;
resets = <&rst FPGA2HPS_RESET>;
clocks = <&l4_main_clk>;
};