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ARM: 8844/1: use unified assembler in assembly files

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Use unified assembler syntax (UAL) in assembly files. Divided
syntax is considered deprecated. This will also allow to build
the kernel using LLVM's integrated assembler.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Stefan Agner 2019-02-18 00:57:38 +01:00 committed by Russell King
parent c001899a5d
commit e44fc38818
31 changed files with 124 additions and 124 deletions
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2
arch/arm/boot/bootp/init.S
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@ -44,7 +44,7 @@ _start: add lr, pc, #-0x8 @ lr = current load addr
*/
movne r10, #0 @ terminator
movne r4, #2 @ Size of this entry (2 words)
stmneia r9, {r4, r5, r10} @ Size, ATAG_CORE, terminator
stmiane r9, {r4, r5, r10} @ Size, ATAG_CORE, terminator
/*
* find the end of the tag list, and then add an INITRD tag on the end.

4
arch/arm/boot/compressed/ll_char_wr.S
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@ -75,7 +75,7 @@ Lrow4bpplp:
tst r1, #7 @ avoid using r7 directly after
str r7, [r0, -r5]!
subne r1, r1, #1
ldrneb r7, [r6, r1]
ldrbne r7, [r6, r1]
bne Lrow4bpplp
ldmfd sp!, {r4 - r7, pc}
@ -103,7 +103,7 @@ Lrow8bpplp:
sub r0, r0, r5 @ avoid ip
stmia r0, {r4, ip}
subne r1, r1, #1
ldrneb r7, [r6, r1]
ldrbne r7, [r6, r1]
bne Lrow8bpplp
ldmfd sp!, {r4 - r7, pc}

10
arch/arm/include/asm/hardware/entry-macro-iomd.S
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@ -16,25 +16,25 @@
ldr \tmp, =irq_prio_h
teq \irqstat, #0
#ifdef IOMD_BASE
ldreqb \irqstat, [\base, #IOMD_DMAREQ] @ get dma
ldrbeq \irqstat, [\base, #IOMD_DMAREQ] @ get dma
addeq \tmp, \tmp, #256 @ irq_prio_h table size
teqeq \irqstat, #0
bne 2406f
#endif
ldreqb \irqstat, [\base, #IOMD_IRQREQA] @ get low priority
ldrbeq \irqstat, [\base, #IOMD_IRQREQA] @ get low priority
addeq \tmp, \tmp, #256 @ irq_prio_d table size
teqeq \irqstat, #0
#ifdef IOMD_IRQREQC
ldreqb \irqstat, [\base, #IOMD_IRQREQC]
ldrbeq \irqstat, [\base, #IOMD_IRQREQC]
addeq \tmp, \tmp, #256 @ irq_prio_l table size
teqeq \irqstat, #0
#endif
#ifdef IOMD_IRQREQD
ldreqb \irqstat, [\base, #IOMD_IRQREQD]
ldrbeq \irqstat, [\base, #IOMD_IRQREQD]
addeq \tmp, \tmp, #256 @ irq_prio_lc table size
teqeq \irqstat, #0
#endif
2406: ldrneb \irqnr, [\tmp, \irqstat] @ get IRQ number
2406: ldrbne \irqnr, [\tmp, \irqstat] @ get IRQ number
.endm
/*

2
arch/arm/include/debug/tegra.S
View File

@ -173,7 +173,7 @@
.macro senduart, rd, rx
cmp \rx, #0
strneb \rd, [\rx, #UART_TX << UART_SHIFT]
strbne \rd, [\rx, #UART_TX << UART_SHIFT]
1001:
.endm

2
arch/arm/kernel/debug.S
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@ -86,7 +86,7 @@ hexbuf_rel: .long hexbuf_addr - .
ENTRY(printascii)
addruart_current r3, r1, r2
1: teq r0, #0
ldrneb r1, [r0], #1
ldrbne r1, [r0], #1
teqne r1, #0
reteq lr
2: teq r1, #'\n'

12
arch/arm/kernel/entry-armv.S
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@ -636,7 +636,7 @@ call_fpe:
@ Test if we need to give access to iWMMXt coprocessors
ldr r5, [r10, #TI_FLAGS]
rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
movscs r7, r5, lsr #(TIF_USING_IWMMXT + 1)
bcs iwmmxt_task_enable
#endif
ARM( add pc, pc, r8, lsr #6 )
@ -872,7 +872,7 @@ __kuser_cmpxchg64: @ 0xffff0f60
smp_dmb arm
1: ldrexd r0, r1, [r2] @ load current val
eors r3, r0, r4 @ compare with oldval (1)
eoreqs r3, r1, r5 @ compare with oldval (2)
eorseq r3, r1, r5 @ compare with oldval (2)
strexdeq r3, r6, r7, [r2] @ store newval if eq
teqeq r3, #1 @ success?
beq 1b @ if no then retry
@ -896,8 +896,8 @@ __kuser_cmpxchg64: @ 0xffff0f60
ldmia r1, {r6, lr} @ load new val
1: ldmia r2, {r0, r1} @ load current val
eors r3, r0, r4 @ compare with oldval (1)
eoreqs r3, r1, r5 @ compare with oldval (2)
2: stmeqia r2, {r6, lr} @ store newval if eq
eorseq r3, r1, r5 @ compare with oldval (2)
2: stmiaeq r2, {r6, lr} @ store newval if eq
rsbs r0, r3, #0 @ set return val and C flag
ldmfd sp!, {r4, r5, r6, pc}
@ -911,7 +911,7 @@ kuser_cmpxchg64_fixup:
mov r7, #0xffff0fff
sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
subs r8, r4, r7
rsbcss r8, r8, #(2b - 1b)
rsbscs r8, r8, #(2b - 1b)
strcs r7, [sp, #S_PC]
#if __LINUX_ARM_ARCH__ < 6
bcc kuser_cmpxchg32_fixup
@ -969,7 +969,7 @@ kuser_cmpxchg32_fixup:
mov r7, #0xffff0fff
sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
subs r8, r4, r7
rsbcss r8, r8, #(2b - 1b)
rsbscs r8, r8, #(2b - 1b)
strcs r7, [sp, #S_PC]
ret lr
.previous

2
arch/arm/kernel/entry-common.S
View File

@ -373,7 +373,7 @@ sys_syscall:
movhs scno, #0
csdb
#endif
stmloia sp, {r5, r6} @ shuffle args
stmialo sp, {r5, r6} @ shuffle args
movlo r0, r1
movlo r1, r2
movlo r2, r3

8
arch/arm/kernel/entry-header.S
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@ -388,8 +388,8 @@
badr lr, \ret @ return address
.if \reload
add r1, sp, #S_R0 + S_OFF @ pointer to regs
ldmccia r1, {r0 - r6} @ reload r0-r6
stmccia sp, {r4, r5} @ update stack arguments
ldmiacc r1, {r0 - r6} @ reload r0-r6
stmiacc sp, {r4, r5} @ update stack arguments
.endif
ldrcc pc, [\table, \tmp, lsl #2] @ call sys_* routine
#else
@ -397,8 +397,8 @@
badr lr, \ret @ return address
.if \reload
add r1, sp, #S_R0 + S_OFF @ pointer to regs
ldmccia r1, {r0 - r6} @ reload r0-r6
stmccia sp, {r4, r5} @ update stack arguments
ldmiacc r1, {r0 - r6} @ reload r0-r6
stmiacc sp, {r4, r5} @ update stack arguments
.endif
ldrcc pc, [\table, \nr, lsl #2] @ call sys_* routine
#endif

2
arch/arm/lib/clear_user.S
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@ -44,7 +44,7 @@ UNWIND(.save {r1, lr})
strusr r2, r0, 1, ne, rept=2
tst r1, #1 @ x1 x0 x1 x0 x1 x0 x1
it ne @ explicit IT needed for the label
USER( strnebt r2, [r0])
USER( strbtne r2, [r0])
mov r0, #0
ldmfd sp!, {r1, pc}
UNWIND(.fnend)

4
arch/arm/lib/copy_page.S
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@ -39,9 +39,9 @@ ENTRY(copy_page)
.endr
subs r2, r2, #1 @ 1
stmia r0!, {r3, r4, ip, lr} @ 4
ldmgtia r1!, {r3, r4, ip, lr} @ 4
ldmiagt r1!, {r3, r4, ip, lr} @ 4
bgt 1b @ 1
PLD( ldmeqia r1!, {r3, r4, ip, lr} )
PLD( ldmiaeq r1!, {r3, r4, ip, lr} )
PLD( beq 2b )
ldmfd sp!, {r4, pc} @ 3
ENDPROC(copy_page)

4
arch/arm/lib/copy_template.S
View File

@ -99,7 +99,7 @@
CALGN( ands ip, r0, #31 )
CALGN( rsb r3, ip, #32 )
CALGN( sbcnes r4, r3, r2 ) @ C is always set here
CALGN( sbcsne r4, r3, r2 ) @ C is always set here
CALGN( bcs 2f )
CALGN( adr r4, 6f )
CALGN( subs r2, r2, r3 ) @ C gets set
@ -204,7 +204,7 @@
CALGN( ands ip, r0, #31 )
CALGN( rsb ip, ip, #32 )
CALGN( sbcnes r4, ip, r2 ) @ C is always set here
CALGN( sbcsne r4, ip, r2 ) @ C is always set here
CALGN( subcc r2, r2, ip )
CALGN( bcc 15f )

20
arch/arm/lib/csumpartial.S
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@ -40,9 +40,9 @@ td3 .req lr
/* we must have at least one byte. */
tst buf, #1 @ odd address?
movne sum, sum, ror #8
ldrneb td0, [buf], #1
ldrbne td0, [buf], #1
subne len, len, #1
adcnes sum, sum, td0, put_byte_1
adcsne sum, sum, td0, put_byte_1
.Lless4: tst len, #6
beq .Lless8_byte
@ -68,8 +68,8 @@ td3 .req lr
bne .Lless8_wordlp
.Lless8_byte: tst len, #1 @ odd number of bytes
ldrneb td0, [buf], #1 @ include last byte
adcnes sum, sum, td0, put_byte_0 @ update checksum
ldrbne td0, [buf], #1 @ include last byte
adcsne sum, sum, td0, put_byte_0 @ update checksum
.Ldone: adc r0, sum, #0 @ collect up the last carry
ldr td0, [sp], #4
@ -78,17 +78,17 @@ td3 .req lr
ldr pc, [sp], #4 @ return
.Lnot_aligned: tst buf, #1 @ odd address
ldrneb td0, [buf], #1 @ make even
ldrbne td0, [buf], #1 @ make even
subne len, len, #1
adcnes sum, sum, td0, put_byte_1 @ update checksum
adcsne sum, sum, td0, put_byte_1 @ update checksum
tst buf, #2 @ 32-bit aligned?
#if __LINUX_ARM_ARCH__ >= 4
ldrneh td0, [buf], #2 @ make 32-bit aligned
ldrhne td0, [buf], #2 @ make 32-bit aligned
subne len, len, #2
#else
ldrneb td0, [buf], #1
ldrneb ip, [buf], #1
ldrbne td0, [buf], #1
ldrbne ip, [buf], #1
subne len, len, #2
#ifndef __ARMEB__
orrne td0, td0, ip, lsl #8
@ -96,7 +96,7 @@ td3 .req lr
orrne td0, ip, td0, lsl #8
#endif
#endif
adcnes sum, sum, td0 @ update checksum
adcsne sum, sum, td0 @ update checksum
ret lr
ENTRY(csum_partial)

4
arch/arm/lib/csumpartialcopygeneric.S
View File

@ -148,9 +148,9 @@ FN_ENTRY
strb r5, [dst], #1
mov r5, r4, get_byte_2
.Lexit: tst len, #1
strneb r5, [dst], #1
strbne r5, [dst], #1
andne r5, r5, #255
adcnes sum, sum, r5, put_byte_0
adcsne sum, sum, r5, put_byte_0
/*
* If the dst pointer was not 16-bit aligned, we

2
arch/arm/lib/csumpartialcopyuser.S
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@ -95,7 +95,7 @@
add r2, r2, r1
mov r0, #0 @ zero the buffer
9002: teq r2, r1
strneb r0, [r1], #1
strbne r0, [r1], #1
bne 9002b
load_regs
.popsection

4
arch/arm/lib/div64.S
View File

@ -88,8 +88,8 @@ UNWIND(.fnstart)
@ Break out early if dividend reaches 0.
2: cmp xh, yl
orrcs yh, yh, ip
subcss xh, xh, yl
movnes ip, ip, lsr #1
subscs xh, xh, yl
movsne ip, ip, lsr #1
mov yl, yl, lsr #1
bne 2b

10
arch/arm/lib/floppydma.S
View File

@ -14,8 +14,8 @@
.global floppy_fiqin_end
ENTRY(floppy_fiqin_start)
subs r9, r9, #1
ldrgtb r12, [r11, #-4]
ldrleb r12, [r11], #0
ldrbgt r12, [r11, #-4]
ldrble r12, [r11], #0
strb r12, [r10], #1
subs pc, lr, #4
floppy_fiqin_end:
@ -23,10 +23,10 @@ floppy_fiqin_end:
.global floppy_fiqout_end
ENTRY(floppy_fiqout_start)
subs r9, r9, #1
ldrgeb r12, [r10], #1
ldrbge r12, [r10], #1
movlt r12, #0
strleb r12, [r11], #0
subles pc, lr, #4
strble r12, [r11], #0
subsle pc, lr, #4
strb r12, [r11, #-4]
subs pc, lr, #4
floppy_fiqout_end:

20
arch/arm/lib/io-readsb.S
View File

@ -16,10 +16,10 @@
cmp ip, #2
ldrb r3, [r0]
strb r3, [r1], #1
ldrgeb r3, [r0]
strgeb r3, [r1], #1
ldrgtb r3, [r0]
strgtb r3, [r1], #1
ldrbge r3, [r0]
strbge r3, [r1], #1
ldrbgt r3, [r0]
strbgt r3, [r1], #1
subs r2, r2, ip
bne .Linsb_aligned
@ -72,7 +72,7 @@ ENTRY(__raw_readsb)
bpl .Linsb_16_lp
tst r2, #15
ldmeqfd sp!, {r4 - r6, pc}
ldmfdeq sp!, {r4 - r6, pc}
.Linsb_no_16: tst r2, #8
beq .Linsb_no_8
@ -109,15 +109,15 @@ ENTRY(__raw_readsb)
str r3, [r1], #4
.Linsb_no_4: ands r2, r2, #3
ldmeqfd sp!, {r4 - r6, pc}
ldmfdeq sp!, {r4 - r6, pc}
cmp r2, #2
ldrb r3, [r0]
strb r3, [r1], #1
ldrgeb r3, [r0]
strgeb r3, [r1], #1
ldrgtb r3, [r0]
strgtb r3, [r1]
ldrbge r3, [r0]
strbge r3, [r1], #1
ldrbgt r3, [r0]
strbgt r3, [r1]
ldmfd sp!, {r4 - r6, pc}
ENDPROC(__raw_readsb)

2
arch/arm/lib/io-readsl.S
View File

@ -30,7 +30,7 @@ ENTRY(__raw_readsl)
2: movs r2, r2, lsl #31
ldrcs r3, [r0, #0]
ldrcs ip, [r0, #0]
stmcsia r1!, {r3, ip}
stmiacs r1!, {r3, ip}
ldrne r3, [r0, #0]
strne r3, [r1, #0]
ret lr

6
arch/arm/lib/io-readsw-armv3.S
View File

@ -68,7 +68,7 @@ ENTRY(__raw_readsw)
bpl .Linsw_8_lp
tst r2, #7
ldmeqfd sp!, {r4, r5, r6, pc}
ldmfdeq sp!, {r4, r5, r6, pc}
.Lno_insw_8: tst r2, #4
beq .Lno_insw_4
@ -97,9 +97,9 @@ ENTRY(__raw_readsw)
.Lno_insw_2: tst r2, #1
ldrne r3, [r0]
strneb r3, [r1], #1
strbne r3, [r1], #1
movne r3, r3, lsr #8
strneb r3, [r1]
strbne r3, [r1]
ldmfd sp!, {r4, r5, r6, pc}

12
arch/arm/lib/io-readsw-armv4.S
View File

@ -76,8 +76,8 @@ ENTRY(__raw_readsw)
pack r3, r3, ip
str r3, [r1], #4
.Lno_insw_2: ldrneh r3, [r0]
strneh r3, [r1]
.Lno_insw_2: ldrhne r3, [r0]
strhne r3, [r1]
ldmfd sp!, {r4, r5, pc}
@ -94,7 +94,7 @@ ENTRY(__raw_readsw)
#endif
.Linsw_noalign: stmfd sp!, {r4, lr}
ldrccb ip, [r1, #-1]!
ldrbcc ip, [r1, #-1]!
bcc 1f
ldrh ip, [r0]
@ -121,11 +121,11 @@ ENTRY(__raw_readsw)
3: tst r2, #1
strb ip, [r1], #1
ldrneh ip, [r0]
ldrhne ip, [r0]
_BE_ONLY_( movne ip, ip, ror #8 )
strneb ip, [r1], #1
strbne ip, [r1], #1
_LE_ONLY_( movne ip, ip, lsr #8 )
_BE_ONLY_( movne ip, ip, lsr #24 )
strneb ip, [r1]
strbne ip, [r1]
ldmfd sp!, {r4, pc}
ENDPROC(__raw_readsw)

20
arch/arm/lib/io-writesb.S
View File

@ -36,10 +36,10 @@
cmp ip, #2
ldrb r3, [r1], #1
strb r3, [r0]
ldrgeb r3, [r1], #1
strgeb r3, [r0]
ldrgtb r3, [r1], #1
strgtb r3, [r0]
ldrbge r3, [r1], #1
strbge r3, [r0]
ldrbgt r3, [r1], #1
strbgt r3, [r0]
subs r2, r2, ip
bne .Loutsb_aligned
@ -64,7 +64,7 @@ ENTRY(__raw_writesb)
bpl .Loutsb_16_lp
tst r2, #15
ldmeqfd sp!, {r4, r5, pc}
ldmfdeq sp!, {r4, r5, pc}
.Loutsb_no_16: tst r2, #8
beq .Loutsb_no_8
@ -80,15 +80,15 @@ ENTRY(__raw_writesb)
outword r3
.Loutsb_no_4: ands r2, r2, #3
ldmeqfd sp!, {r4, r5, pc}
ldmfdeq sp!, {r4, r5, pc}
cmp r2, #2
ldrb r3, [r1], #1
strb r3, [r0]
ldrgeb r3, [r1], #1
strgeb r3, [r0]
ldrgtb r3, [r1]
strgtb r3, [r0]
ldrbge r3, [r1], #1
strbge r3, [r0]
ldrbgt r3, [r1]
strbgt r3, [r0]
ldmfd sp!, {r4, r5, pc}
ENDPROC(__raw_writesb)

2
arch/arm/lib/io-writesl.S
View File

@ -28,7 +28,7 @@ ENTRY(__raw_writesl)
bpl 1b
ldmfd sp!, {r4, lr}
2: movs r2, r2, lsl #31
ldmcsia r1!, {r3, ip}
ldmiacs r1!, {r3, ip}
strcs r3, [r0, #0]
ldrne r3, [r1, #0]
strcs ip, [r0, #0]

2
arch/arm/lib/io-writesw-armv3.S
View File

@ -79,7 +79,7 @@ ENTRY(__raw_writesw)
bpl .Loutsw_8_lp
tst r2, #7
ldmeqfd sp!, {r4, r5, r6, pc}
ldmfdeq sp!, {r4, r5, r6, pc}
.Lno_outsw_8: tst r2, #4
beq .Lno_outsw_4

6
arch/arm/lib/io-writesw-armv4.S
View File

@ -61,8 +61,8 @@ ENTRY(__raw_writesw)
ldr r3, [r1], #4
outword r3
.Lno_outsw_2: ldrneh r3, [r1]
strneh r3, [r0]
.Lno_outsw_2: ldrhne r3, [r1]
strhne r3, [r0]
ldmfd sp!, {r4, r5, pc}
@ -95,6 +95,6 @@ ENTRY(__raw_writesw)
tst r2, #1
3: movne ip, r3, lsr #8
strneh ip, [r0]
strhne ip, [r0]
ret lr
ENDPROC(__raw_writesw)

4
arch/arm/lib/lib1funcs.S
View File

@ -96,7 +96,7 @@ Boston, MA 02111-1307, USA. */
subhs \dividend, \dividend, \divisor, lsr #3
orrhs \result, \result, \curbit, lsr #3
cmp \dividend, #0 @ Early termination?
movnes \curbit, \curbit, lsr #4 @ No, any more bits to do?
movsne \curbit, \curbit, lsr #4 @ No, any more bits to do?
movne \divisor, \divisor, lsr #4
bne 1b
@ -182,7 +182,7 @@ Boston, MA 02111-1307, USA. */
subhs \dividend, \dividend, \divisor, lsr #3
cmp \dividend, #1
mov \divisor, \divisor, lsr #4
subges \order, \order, #4
subsge \order, \order, #4
bge 1b
tst \order, #3

24
arch/arm/lib/memmove.S
View File

@ -59,7 +59,7 @@ ENTRY(memmove)
blt 5f
CALGN( ands ip, r0, #31 )
CALGN( sbcnes r4, ip, r2 ) @ C is always set here
CALGN( sbcsne r4, ip, r2 ) @ C is always set here
CALGN( bcs 2f )
CALGN( adr r4, 6f )
CALGN( subs r2, r2, ip ) @ C is set here
@ -114,20 +114,20 @@ ENTRY(memmove)
UNWIND( .save {r0, r4, lr} ) @ still in first stmfd block
8: movs r2, r2, lsl #31
ldrneb r3, [r1, #-1]!
ldrcsb r4, [r1, #-1]!
ldrcsb ip, [r1, #-1]
strneb r3, [r0, #-1]!
strcsb r4, [r0, #-1]!
strcsb ip, [r0, #-1]
ldrbne r3, [r1, #-1]!
ldrbcs r4, [r1, #-1]!
ldrbcs ip, [r1, #-1]
strbne r3, [r0, #-1]!
strbcs r4, [r0, #-1]!
strbcs ip, [r0, #-1]
ldmfd sp!, {r0, r4, pc}
9: cmp ip, #2
ldrgtb r3, [r1, #-1]!
ldrgeb r4, [r1, #-1]!
ldrbgt r3, [r1, #-1]!
ldrbge r4, [r1, #-1]!
ldrb lr, [r1, #-1]!
strgtb r3, [r0, #-1]!
strgeb r4, [r0, #-1]!
strbgt r3, [r0, #-1]!
strbge r4, [r0, #-1]!
subs r2, r2, ip
strb lr, [r0, #-1]!
blt 8b
@ -150,7 +150,7 @@ ENTRY(memmove)
blt 14f
CALGN( ands ip, r0, #31 )
CALGN( sbcnes r4, ip, r2 ) @ C is always set here
CALGN( sbcsne r4, ip, r2 ) @ C is always set here
CALGN( subcc r2, r2, ip )
CALGN( bcc 15f )

42
arch/arm/lib/memset.S
View File

@ -44,20 +44,20 @@ UNWIND( .save {r8, lr} )
mov lr, r3
2: subs r2, r2, #64
stmgeia ip!, {r1, r3, r8, lr} @ 64 bytes at a time.
stmgeia ip!, {r1, r3, r8, lr}
stmgeia ip!, {r1, r3, r8, lr}
stmgeia ip!, {r1, r3, r8, lr}
stmiage ip!, {r1, r3, r8, lr} @ 64 bytes at a time.
stmiage ip!, {r1, r3, r8, lr}
stmiage ip!, {r1, r3, r8, lr}
stmiage ip!, {r1, r3, r8, lr}
bgt 2b
ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go.
ldmfdeq sp!, {r8, pc} @ Now <64 bytes to go.
/*
* No need to correct the count; we're only testing bits from now on
*/
tst r2, #32
stmneia ip!, {r1, r3, r8, lr}
stmneia ip!, {r1, r3, r8, lr}
stmiane ip!, {r1, r3, r8, lr}
stmiane ip!, {r1, r3, r8, lr}
tst r2, #16
stmneia ip!, {r1, r3, r8, lr}
stmiane ip!, {r1, r3, r8, lr}
ldmfd sp!, {r8, lr}
UNWIND( .fnend )
@ -87,22 +87,22 @@ UNWIND( .save {r4-r8, lr} )
rsb r8, r8, #32
sub r2, r2, r8
movs r8, r8, lsl #(32 - 4)
stmcsia ip!, {r4, r5, r6, r7}
stmmiia ip!, {r4, r5}
stmiacs ip!, {r4, r5, r6, r7}
stmiami ip!, {r4, r5}
tst r8, #(1 << 30)
mov r8, r1
strne r1, [ip], #4
3: subs r2, r2, #64
stmgeia ip!, {r1, r3-r8, lr}
stmgeia ip!, {r1, r3-r8, lr}
stmiage ip!, {r1, r3-r8, lr}
stmiage ip!, {r1, r3-r8, lr}
bgt 3b
ldmeqfd sp!, {r4-r8, pc}
ldmfdeq sp!, {r4-r8, pc}
tst r2, #32
stmneia ip!, {r1, r3-r8, lr}
stmiane ip!, {r1, r3-r8, lr}
tst r2, #16
stmneia ip!, {r4-r7}
stmiane ip!, {r4-r7}
ldmfd sp!, {r4-r8, lr}
UNWIND( .fnend )
@ -110,7 +110,7 @@ UNWIND( .fnend )
UNWIND( .fnstart )
4: tst r2, #8
stmneia ip!, {r1, r3}
stmiane ip!, {r1, r3}
tst r2, #4
strne r1, [ip], #4
/*
@ -118,17 +118,17 @@ UNWIND( .fnstart )
* may have an unaligned pointer as well.
*/
5: tst r2, #2
strneb r1, [ip], #1
strneb r1, [ip], #1
strbne r1, [ip], #1
strbne r1, [ip], #1
tst r2, #1
strneb r1, [ip], #1
strbne r1, [ip], #1
ret lr
6: subs r2, r2, #4 @ 1 do we have enough
blt 5b @ 1 bytes to align with?
cmp r3, #2 @ 1
strltb r1, [ip], #1 @ 1
strleb r1, [ip], #1 @ 1
strblt r1, [ip], #1 @ 1
strble r1, [ip], #1 @ 1
strb r1, [ip], #1 @ 1
add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
b 1b

2
arch/arm/mach-ks8695/include/mach/entry-macro.S
View File

@ -42,6 +42,6 @@
moveq \irqstat, \irqstat, lsr #2
addeq \irqnr, \irqnr, #2
tst \irqstat, #0x01
addeqs \irqnr, \irqnr, #1
addseq \irqnr, \irqnr, #1
1001:
.endm

2
arch/arm/mach-tegra/reset-handler.S
View File

@ -172,7 +172,7 @@ after_errata:
mov32 r5, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET
mov r0, #CPU_NOT_RESETTABLE
cmp r10, #0
strneb r0, [r5, #__tegra20_cpu1_resettable_status_offset]
strbne r0, [r5, #__tegra20_cpu1_resettable_status_offset]
1:
#endif

8
arch/arm/mm/cache-v6.S
View File

@ -215,8 +215,8 @@ v6_dma_inv_range:
#endif
tst r1, #D_CACHE_LINE_SIZE - 1
#ifdef CONFIG_DMA_CACHE_RWFO
ldrneb r2, [r1, #-1] @ read for ownership
strneb r2, [r1, #-1] @ write for ownership
ldrbne r2, [r1, #-1] @ read for ownership
strbne r2, [r1, #-1] @ write for ownership
#endif
bic r1, r1, #D_CACHE_LINE_SIZE - 1
#ifdef HARVARD_CACHE
@ -284,8 +284,8 @@ ENTRY(v6_dma_flush_range)
add r0, r0, #D_CACHE_LINE_SIZE
cmp r0, r1
#ifdef CONFIG_DMA_CACHE_RWFO
ldrlob r2, [r0] @ read for ownership
strlob r2, [r0] @ write for ownership
ldrblo r2, [r0] @ read for ownership
strblo r2, [r0] @ write for ownership
#endif
blo 1b
mov r0, #0

4
arch/arm/mm/proc-v7m.S
View File

@ -152,10 +152,10 @@ __v7m_setup_cont:
@ Configure caches (if implemented)
teq r8, #0
stmneia sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6
stmiane sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6
blne v7m_invalidate_l1
teq r8, #0 @ re-evalutae condition
ldmneia sp, {r0-r6, lr}
ldmiane sp, {r0-r6, lr}
@ Configure the System Control Register to ensure 8-byte stack alignment
@ Note the STKALIGN bit is either RW or RAO.