forked from luck/tmp_suning_uos_patched
mx25: fix clock's calculation
* get_rate_arm : when 400MHz clock is selected (cctl & 1<<14), ARM clock is 400MHz (MPLL * 3 / 4) and not 800MHz * get_rate_per : peripherals's clock is derived from AHB and not from IPG (ref manual : figure 5-1) * can2_clk : use the correct ID * without this patch, peripherals getting their clock from PER clocks work fine because of the 2 errors which fix themselves (ARM clock x 2 and per clock actually based on IPG which is AHB/2) but flexcan can't work as it gets its clock from IPG and thus calculates its bitrate using a reference value which is twice what it really is. Signed-off-by: Eric Bénard <eric@eukrea.com>
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@ -72,7 +72,7 @@ unsigned long get_rate_arm(struct clk *clk)
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unsigned long rate = get_rate_mpll();
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if (cctl & (1 << 14))
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rate = (rate * 3) >> 1;
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rate = (rate * 3) >> 2;
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return rate / ((cctl >> 30) + 1);
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}
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@ -99,7 +99,7 @@ static unsigned long get_rate_per(int per)
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if (readl(CRM_BASE + 0x64) & (1 << per))
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fref = get_rate_upll();
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else
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fref = get_rate_ipg(NULL);
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fref = get_rate_ahb(NULL);
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return fref / (val + 1);
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}
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@ -261,7 +261,7 @@ DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGCR1, 14, get_rate_esdhc2, NULL,
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DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
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DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk);
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DEFINE_CLOCK(can1_clk, 0, CCM_CGCR1, 2, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(can2_clk, 0, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(can2_clk, 1, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL);
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#define _REGISTER_CLOCK(d, n, c) \
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{ \
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