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MIPS: BCM63XX: fix BCM6345 clocks bits

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BCM6345 has an intermediate 16-bits wide test control register between the
peripheral identifier register, and its clock control register is only 16-bits
wide contrary to other platforms where it is 32-bits wide. By shifting all
clocks bits by 16-bits to the left we ensure they get written to the proper
clock control register, without adding specific BCM6345 handling in the clock
code.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4555/
Signed-off-by: John Crispin <blogic@openwrt.org>
This commit is contained in:
Florian Fainelli 2012-11-12 08:48:45 +00:00 committed by John Crispin
parent 0224cde212
commit e59b008e14
1 changed files with 12 additions and 7 deletions
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19
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@ -53,13 +53,18 @@
CKCTL_6338_SAR_EN | \
CKCTL_6338_SPI_EN)
#define CKCTL_6345_CPU_EN (1 << 0)
#define CKCTL_6345_BUS_EN (1 << 1)
#define CKCTL_6345_EBI_EN (1 << 2)
#define CKCTL_6345_UART_EN (1 << 3)
#define CKCTL_6345_ADSLPHY_EN (1 << 4)
#define CKCTL_6345_ENET_EN (1 << 7)
#define CKCTL_6345_USBH_EN (1 << 8)
/* BCM6345 clock bits are shifted by 16 on the left, because of the test
* control register which is 16-bits wide. That way we do not have any
* specific BCM6345 code for handling clocks, and writing 0 to the test
* control register is fine.
*/
#define CKCTL_6345_CPU_EN (1 << 16)
#define CKCTL_6345_BUS_EN (1 << 17)
#define CKCTL_6345_EBI_EN (1 << 18)
#define CKCTL_6345_UART_EN (1 << 19)
#define CKCTL_6345_ADSLPHY_EN (1 << 20)
#define CKCTL_6345_ENET_EN (1 << 23)
#define CKCTL_6345_USBH_EN (1 << 24)
#define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \
CKCTL_6345_USBH_EN | \