forked from luck/tmp_suning_uos_patched
nvme: simplify stripe quirk
Some OEMs believe they own the Identify Controller vendor specific region and will repurpose it with their own values. While not common, we can't rely on the PCI VID:DID to tell use how to decode the field we reserved for this as the stripe size so we need to do something else for the list of devices using this quirk. The field was supposed to allow flexibility on the device's back-end striping, but it turned out that never materialized; the chunk is always the same as MDTS in the products subscribing to this quirk, so this patch removes the stripe_size field and sets the chunk to the max hw transfer size for the devices using this quirk. Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Christoph Hellwig <hch@lst.de>
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@ -1193,8 +1193,8 @@ static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
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blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
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blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
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}
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if (ctrl->stripe_size)
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blk_queue_chunk_sectors(q, ctrl->stripe_size >> 9);
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if (ctrl->quirks & NVME_QUIRK_STRIPE_SIZE)
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blk_queue_chunk_sectors(q, ctrl->max_hw_sectors);
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blk_queue_virt_boundary(q, ctrl->page_size - 1);
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if (ctrl->vwc & NVME_CTRL_VWC_PRESENT)
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vwc = true;
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@ -1250,19 +1250,6 @@ int nvme_init_identify(struct nvme_ctrl *ctrl)
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ctrl->max_hw_sectors =
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min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
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if ((ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) && id->vs[3]) {
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unsigned int max_hw_sectors;
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ctrl->stripe_size = 1 << (id->vs[3] + page_shift);
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max_hw_sectors = ctrl->stripe_size >> (page_shift - 9);
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if (ctrl->max_hw_sectors) {
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ctrl->max_hw_sectors = min(max_hw_sectors,
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ctrl->max_hw_sectors);
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} else {
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ctrl->max_hw_sectors = max_hw_sectors;
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}
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}
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nvme_set_queue_limits(ctrl, ctrl->admin_q);
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ctrl->sgls = le32_to_cpu(id->sgls);
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ctrl->kas = le16_to_cpu(id->kas);
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@ -135,7 +135,6 @@ struct nvme_ctrl {
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u32 page_size;
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u32 max_hw_sectors;
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u32 stripe_size;
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u16 oncs;
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u16 vid;
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atomic_t abort_limit;
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