forked from luck/tmp_suning_uos_patched
ARM: sirf: drop Marco support in reset controller module
Marco will not be supported any more. It has been replaced by CSR Atlas7. Signed-off-by: Barry Song <Baohua.Song@csr.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
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@ -34,36 +34,20 @@ static int sirfsoc_reset_module(struct reset_controller_dev *rcdev,
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mutex_lock(&rstc_lock);
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if (of_device_is_compatible(rcdev->of_node, "sirf,prima2-rstc")) {
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/*
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* Writing 1 to this bit resets corresponding block.
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* Writing 0 to this bit de-asserts reset signal of the
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* corresponding block. datasheet doesn't require explicit
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* delay between the set and clear of reset bit. it could
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* be shorter if tests pass.
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*/
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writel(readl(sirfsoc_rstc_base +
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/*
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* Writing 1 to this bit resets corresponding block.
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* Writing 0 to this bit de-asserts reset signal of the
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* corresponding block. datasheet doesn't require explicit
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* delay between the set and clear of reset bit. it could
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* be shorter if tests pass.
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*/
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writel(readl(sirfsoc_rstc_base +
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(reset_bit / 32) * 4) | (1 << reset_bit),
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sirfsoc_rstc_base + (reset_bit / 32) * 4);
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msleep(20);
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writel(readl(sirfsoc_rstc_base +
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sirfsoc_rstc_base + (reset_bit / 32) * 4);
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msleep(20);
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writel(readl(sirfsoc_rstc_base +
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(reset_bit / 32) * 4) & ~(1 << reset_bit),
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sirfsoc_rstc_base + (reset_bit / 32) * 4);
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} else {
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/*
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* For MARCO and POLO
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* Writing 1 to SET register resets corresponding block.
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* Writing 1 to CLEAR register de-asserts reset signal of the
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* corresponding block.
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* datasheet doesn't require explicit delay between the set and
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* clear of reset bit. it could be shorter if tests pass.
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*/
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writel(1 << reset_bit,
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sirfsoc_rstc_base + (reset_bit / 32) * 8);
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msleep(20);
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writel(1 << reset_bit,
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sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
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}
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sirfsoc_rstc_base + (reset_bit / 32) * 4);
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mutex_unlock(&rstc_lock);
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@ -106,7 +90,6 @@ static int sirfsoc_rstc_probe(struct platform_device *pdev)
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static const struct of_device_id rstc_ids[] = {
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{ .compatible = "sirf,prima2-rstc" },
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{ .compatible = "sirf,marco-rstc" },
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{},
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};
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