forked from luck/tmp_suning_uos_patched
r8169: more 8168dp support.
Adapted from version 8.019.00 of Realtek's r8168 driver Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Cc: Hayes <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
françois romieu
David S. Miller
parent
650e8d5d1f
commit
e6de30d63e
@ -121,7 +121,8 @@ enum mac_version {
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RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
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RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
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RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
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RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
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RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
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RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
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};
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#define _R(NAME,MAC,MASK) \
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@ -158,7 +159,8 @@ static const struct {
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_R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
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_R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
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_R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
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_R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
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_R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
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_R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880) // PCI-E
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};
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#undef _R
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@ -301,6 +303,7 @@ enum rtl8168_registers {
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#define OCPAR_FLAG 0x80000000
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#define OCPAR_GPHY_WRITE_CMD 0x8000f060
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#define OCPAR_GPHY_READ_CMD 0x0000f060
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RDSAR1 = 0xd0 /* 8168c only. Undocumented on 8168dp */
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};
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enum rtl_register_content {
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@ -748,6 +751,40 @@ static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
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return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
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}
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#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
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static void r8168dp_2_mdio_start(void __iomem *ioaddr)
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{
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RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
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}
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static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
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{
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RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
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}
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static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
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{
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r8168dp_2_mdio_start(ioaddr);
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r8169_mdio_write(ioaddr, reg_addr, value);
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r8168dp_2_mdio_stop(ioaddr);
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}
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static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
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{
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int value;
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r8168dp_2_mdio_start(ioaddr);
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value = r8169_mdio_read(ioaddr, reg_addr);
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r8168dp_2_mdio_stop(ioaddr);
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return value;
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}
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static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
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{
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tp->mdio_ops.write(tp->mmio_addr, location, val);
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@ -1495,9 +1532,12 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp,
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/* 8168D family. */
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{ 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
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{ 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
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{ 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
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{ 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
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/* 8168DP family. */
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{ 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
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{ 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
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/* 8168C family. */
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{ 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
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{ 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
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@ -2246,6 +2286,22 @@ static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
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rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
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}
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static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
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{
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static const struct phy_reg phy_reg_init[] = {
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{ 0x1f, 0x0001 },
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{ 0x17, 0x0cc0 },
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{ 0x1f, 0x0007 },
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{ 0x1e, 0x002d },
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{ 0x18, 0x0040 },
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{ 0x1f, 0x0000 }
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};
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rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
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rtl_patchphy(tp, 0x0d, 1 << 5);
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}
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static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
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{
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static const struct phy_reg phy_reg_init[] = {
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@ -2327,6 +2383,9 @@ static void rtl_hw_phy_config(struct net_device *dev)
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case RTL_GIGA_MAC_VER_27:
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rtl8168d_3_hw_phy_config(tp);
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break;
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case RTL_GIGA_MAC_VER_28:
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rtl8168d_4_hw_phy_config(tp);
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break;
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default:
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break;
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@ -2636,6 +2695,10 @@ static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
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ops->write = r8168dp_1_mdio_write;
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ops->read = r8168dp_1_mdio_read;
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break;
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case RTL_GIGA_MAC_VER_28:
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ops->write = r8168dp_2_mdio_write;
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ops->read = r8168dp_2_mdio_read;
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break;
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default:
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ops->write = r8169_mdio_write;
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ops->read = r8169_mdio_read;
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@ -2778,6 +2841,7 @@ static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
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case RTL_GIGA_MAC_VER_25:
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case RTL_GIGA_MAC_VER_26:
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case RTL_GIGA_MAC_VER_27:
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case RTL_GIGA_MAC_VER_28:
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ops->down = r8168_pll_power_down;
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ops->up = r8168_pll_power_up;
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break;
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@ -3000,8 +3064,10 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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dev->base_addr, dev->dev_addr,
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(u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
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if (tp->mac_version == RTL_GIGA_MAC_VER_27)
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if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
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(tp->mac_version == RTL_GIGA_MAC_VER_28)) {
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rtl8168_driver_start(tp);
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}
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rtl8169_init_phy(dev, tp);
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@ -3038,8 +3104,10 @@ static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
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struct net_device *dev = pci_get_drvdata(pdev);
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struct rtl8169_private *tp = netdev_priv(dev);
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if (tp->mac_version == RTL_GIGA_MAC_VER_27)
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if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
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(tp->mac_version == RTL_GIGA_MAC_VER_28)) {
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rtl8168_driver_stop(tp);
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}
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cancel_delayed_work_sync(&tp->task);
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@ -3122,11 +3190,19 @@ static int rtl8169_open(struct net_device *dev)
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goto out;
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}
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static void rtl8169_hw_reset(void __iomem *ioaddr)
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static void rtl8169_hw_reset(struct rtl8169_private *tp)
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{
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void __iomem *ioaddr = tp->mmio_addr;
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/* Disable interrupts */
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rtl8169_irq_mask_and_ack(ioaddr);
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if (tp->mac_version == RTL_GIGA_MAC_VER_28) {
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while (RTL_R8(TxPoll) & NPQ)
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udelay(20);
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}
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/* Reset the chipset */
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RTL_W8(ChipCmd, CmdReset);
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@ -3318,6 +3394,11 @@ static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
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rtl_csi_write(ioaddr, 0x070c, csi | bits);
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}
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static void rtl_csi_access_enable_1(void __iomem *ioaddr)
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{
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rtl_csi_access_enable(ioaddr, 0x17000000);
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}
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static void rtl_csi_access_enable_2(void __iomem *ioaddr)
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{
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rtl_csi_access_enable(ioaddr, 0x27000000);
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@ -3355,6 +3436,21 @@ static void rtl_disable_clock_request(struct pci_dev *pdev)
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}
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}
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static void rtl_enable_clock_request(struct pci_dev *pdev)
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{
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struct net_device *dev = pci_get_drvdata(pdev);
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struct rtl8169_private *tp = netdev_priv(dev);
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int cap = tp->pcie_cap;
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if (cap) {
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u16 ctl;
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pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
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ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
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pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
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}
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}
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#define R8168_CPCMD_QUIRK_MASK (\
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EnableBist | \
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Mac_dbgo_oe | \
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@ -3498,6 +3594,32 @@ static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
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RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
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}
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static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
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{
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static const struct ephy_info e_info_8168d_4[] = {
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{ 0x0b, ~0, 0x48 },
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{ 0x19, 0x20, 0x50 },
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{ 0x0c, ~0, 0x20 }
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};
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int i;
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rtl_csi_access_enable_1(ioaddr);
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rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
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RTL_W8(MaxTxPacketSize, TxPacketMax);
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for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
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const struct ephy_info *e = e_info_8168d_4 + i;
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u16 w;
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w = rtl_ephy_read(ioaddr, e->offset);
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rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
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}
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rtl_enable_clock_request(pdev);
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}
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static void rtl_hw_start_8168(struct net_device *dev)
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{
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struct rtl8169_private *tp = netdev_priv(dev);
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@ -3575,6 +3697,10 @@ static void rtl_hw_start_8168(struct net_device *dev)
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rtl_hw_start_8168d(ioaddr, pdev);
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break;
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case RTL_GIGA_MAC_VER_28:
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rtl_hw_start_8168d_4(ioaddr, pdev);
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break;
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default:
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printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
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dev->name, tp->mac_version);
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@ -3987,7 +4113,7 @@ static void rtl8169_tx_timeout(struct net_device *dev)
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{
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struct rtl8169_private *tp = netdev_priv(dev);
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rtl8169_hw_reset(tp->mmio_addr);
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rtl8169_hw_reset(tp);
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/* Let's wait a bit while any (async) irq lands on */
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rtl8169_schedule_work(dev, rtl8169_reset_task);
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@ -4145,7 +4271,6 @@ static void rtl8169_pcierr_interrupt(struct net_device *dev)
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{
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struct rtl8169_private *tp = netdev_priv(dev);
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struct pci_dev *pdev = tp->pci_dev;
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void __iomem *ioaddr = tp->mmio_addr;
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u16 pci_status, pci_cmd;
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pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
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@ -4176,13 +4301,15 @@ static void rtl8169_pcierr_interrupt(struct net_device *dev)
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/* The infamous DAC f*ckup only happens at boot time */
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if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
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void __iomem *ioaddr = tp->mmio_addr;
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netif_info(tp, intr, dev, "disabling PCI DAC\n");
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tp->cp_cmd &= ~PCIDAC;
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RTL_W16(CPlusCmd, tp->cp_cmd);
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dev->features &= ~NETIF_F_HIGHDMA;
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}
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rtl8169_hw_reset(ioaddr);
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rtl8169_hw_reset(tp);
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rtl8169_schedule_work(dev, rtl8169_reinit_task);
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}
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