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clk: tegra: divider: Mark Memory Controller clock as read-only

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The Memory Controller (MC) clock rate can't be simply changed and nothing
in kernel need to change the rate, hence let's make the clock read-only.
This id also needed for the EMC driver because timing configuration may
require the MC clock diver to be disabled, that is handled by the EMC
clock / EMC driver integration and CLK framework shall not touch the
MC divider configuration on the EMC clock rate change.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Dmitry Osipenko 2019-04-14 22:23:21 +03:00 committed by Stephen Boyd
parent f4037654a8
commit e71f4d3858
1 changed files with 2 additions and 1 deletions
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3
drivers/clk/tegra/clk-divider.c
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@ -175,6 +175,7 @@ struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
void __iomem *reg, spinlock_t *lock) void __iomem *reg, spinlock_t *lock)
{ {
return clk_register_divider_table(NULL, name, parent_name, return clk_register_divider_table(NULL, name, parent_name,
CLK_IS_CRITICAL, reg, 16, 1, 0, CLK_IS_CRITICAL,
reg, 16, 1, CLK_DIVIDER_READ_ONLY,
mc_div_table, lock); mc_div_table, lock);
} }