forked from luck/tmp_suning_uos_patched
sh: Support explicit L1 cache disabling.
This reworks the cache mode configuration in Kconfig, and allows for explicit selection of write-back/write-through/off configurations. All of the cache flushing routines are optimized away for the off case. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
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ac919986d7
commit
e7bd34a15b
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@ -143,12 +143,15 @@ static void __init cache_init(void)
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flags &= ~CCR_CACHE_EMODE;
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#endif
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#ifdef CONFIG_SH_WRITETHROUGH
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/* Turn on Write-through caching */
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#if defined(CONFIG_CACHE_WRITETHROUGH)
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/* Write-through */
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flags |= CCR_CACHE_WT;
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#else
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/* .. or default to Write-back */
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#elif defined(CONFIG_CACHE_WRITEBACK)
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/* Write-back */
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flags |= CCR_CACHE_CB;
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#else
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/* Off */
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flags &= ~CCR_CACHE_ENABLE;
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#endif
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ctrl_outl(flags, CCR);
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@ -128,7 +128,8 @@ DECLARE_EXPORT(__movstrSI12_i4);
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#endif /* __GNUC__ == 4 */
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#endif
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#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
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#if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \
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defined(CONFIG_SH7705_CACHE_32KB))
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/* needed by some modules */
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EXPORT_SYMBOL(flush_cache_all);
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EXPORT_SYMBOL(flush_cache_range);
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@ -136,8 +137,8 @@ EXPORT_SYMBOL(flush_dcache_page);
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EXPORT_SYMBOL(__flush_purge_region);
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#endif
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#if defined(CONFIG_MMU) && (defined(CONFIG_CPU_SH4) || \
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defined(CONFIG_SH7705_CACHE_32KB))
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#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) && \
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(defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB))
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EXPORT_SYMBOL(clear_user_page);
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#endif
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@ -2,7 +2,6 @@
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# Processor families
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#
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config CPU_SH2
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select SH_WRITETHROUGH if !CPU_SH2A
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bool
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config CPU_SH2A
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@ -414,8 +413,17 @@ config SH_DIRECT_MAPPED
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Turn this option off for platforms that do not have a direct-mapped
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cache, and you have no need to run the caches in such a configuration.
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config SH_WRITETHROUGH
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bool "Use write-through caching"
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choice
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prompt "Cache mode"
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default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4
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default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
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config CACHE_WRITEBACK
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bool "Write-back"
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depends on CPU_SH2A || CPU_SH3 || CPU_SH4
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config CACHE_WRITETHROUGH
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bool "Write-through"
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help
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Selecting this option will configure the caches in write-through
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mode, as opposed to the default write-back configuration.
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@ -426,4 +434,9 @@ config SH_WRITETHROUGH
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If unsure, say N.
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config CACHE_OFF
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bool "Off"
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endchoice
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endmenu
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@ -4,9 +4,10 @@
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obj-y := init.o extable.o consistent.o
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obj-$(CONFIG_CPU_SH2) += cache-sh2.o
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obj-$(CONFIG_CPU_SH3) += cache-sh3.o
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obj-$(CONFIG_CPU_SH4) += cache-sh4.o
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cache-$(CONFIG_CPU_SH2) := cache-sh2.o
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cache-$(CONFIG_CPU_SH3) := cache-sh3.o
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cache-$(CONFIG_CPU_SH4) := cache-sh4.o pg-sh4.o
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cache-$(CONFIG_CACHE_OFF) :=
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mmu-y := tlb-nommu.o pg-nommu.o
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mmu-$(CONFIG_CPU_SH3) += fault-nommu.o
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@ -14,7 +15,7 @@ mmu-$(CONFIG_CPU_SH4) += fault-nommu.o
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mmu-$(CONFIG_MMU) := fault.o clear_page.o copy_page.o tlb-flush.o \
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ioremap.o
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obj-y += $(mmu-y)
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obj-y += $(cache-y) $(mmu-y)
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ifdef CONFIG_DEBUG_FS
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obj-$(CONFIG_CPU_SH4) += cache-debugfs.o
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@ -22,7 +23,7 @@ endif
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ifdef CONFIG_MMU
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obj-$(CONFIG_CPU_SH3) += tlb-sh3.o
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obj-$(CONFIG_CPU_SH4) += tlb-sh4.o pg-sh4.o
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obj-$(CONFIG_CPU_SH4) += tlb-sh4.o
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obj-$(CONFIG_SH7705_CACHE_32KB) += pg-sh7705.o
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endif
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@ -145,7 +145,7 @@ int __set_pmb_entry(unsigned long vpn, unsigned long ppn,
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ctrl_outl(vpn | PMB_V, mk_pmb_addr(pos));
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#ifdef CONFIG_SH_WRITETHROUGH
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#ifdef CONFIG_CACHE_WRITETHROUGH
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/*
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* When we are in 32-bit address extended mode, CCR.CB becomes
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* invalid, so care must be taken to manually adjust cacheable
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@ -34,22 +34,27 @@ void update_mmu_cache(struct vm_area_struct * vma,
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unsigned long flags;
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unsigned long pteval;
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unsigned long vpn;
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struct page *page;
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unsigned long pfn;
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/* Ptrace may call this routine. */
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if (vma && current->active_mm != vma->vm_mm)
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return;
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pfn = pte_pfn(pte);
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if (pfn_valid(pfn)) {
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page = pfn_to_page(pfn);
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if (!test_bit(PG_mapped, &page->flags)) {
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unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
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__flush_wback_region((void *)P1SEGADDR(phys), PAGE_SIZE);
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__set_bit(PG_mapped, &page->flags);
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#ifndef CONFIG_CACHE_OFF
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{
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unsigned long pfn = pte_pfn(pte);
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if (pfn_valid(pfn)) {
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struct page *page = pfn_to_page(pfn);
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if (!test_bit(PG_mapped, &page->flags)) {
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unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
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__flush_wback_region((void *)P1SEGADDR(phys),
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PAGE_SIZE);
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__set_bit(PG_mapped, &page->flags);
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}
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}
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}
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#endif
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local_irq_save(flags);
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@ -66,7 +71,7 @@ void update_mmu_cache(struct vm_area_struct * vma,
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/* Set PTEL register */
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pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
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#ifdef CONFIG_SH_WRITETHROUGH
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#ifdef CONFIG_CACHE_WRITETHROUGH
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pteval |= _PAGE_WT;
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#endif
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/* conveniently, we want all the software flags to be 0 anyway */
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@ -1,16 +1,47 @@
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#ifndef __ASM_SH_CACHEFLUSH_H
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#define __ASM_SH_CACHEFLUSH_H
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#ifdef __KERNEL__
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#include <linux/mm.h>
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#ifdef CONFIG_CACHE_OFF
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/*
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* Nothing to do when the cache is disabled, initial flush and explicit
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* disabling is handled at CPU init time.
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*
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* See arch/sh/kernel/cpu/init.c:cache_init().
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*/
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#define p3_cache_init() do { } while (0)
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define flush_dcache_page(page) do { } while (0)
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#define flush_icache_range(start, end) do { } while (0)
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#define flush_icache_page(vma,pg) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define flush_cache_sigtramp(vaddr) do { } while (0)
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#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
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#define __flush_wback_region(start, size) do { (void)(start); } while (0)
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#define __flush_purge_region(start, size) do { (void)(start); } while (0)
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#define __flush_invalidate_region(start, size) do { (void)(start); } while (0)
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#else
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#include <asm/cpu/cacheflush.h>
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/*
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* Consistent DMA requires that the __flush_xxx() primitives must be set
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* for any of the enabled non-coherent caches (most of the UP CPUs),
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* regardless of PIPT or VIPT cache configurations.
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*/
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/* Flush (write-back only) a region (smaller than a page) */
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extern void __flush_wback_region(void *start, int size);
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/* Flush (write-back & invalidate) a region (smaller than a page) */
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extern void __flush_purge_region(void *start, int size);
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/* Flush (invalidate only) a region (smaller than a page) */
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extern void __flush_invalidate_region(void *start, int size);
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#endif
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#define flush_cache_vmap(start, end) flush_cache_all()
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#define flush_cache_vunmap(start, end) flush_cache_all()
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@ -70,14 +70,14 @@ extern void clear_page_nommu(void *to);
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extern void copy_page_nommu(void *to, void *from);
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#endif
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#if defined(CONFIG_MMU) && (defined(CONFIG_CPU_SH4) || \
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defined(CONFIG_SH7705_CACHE_32KB))
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#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) && \
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(defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB))
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struct page;
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extern void clear_user_page(void *to, unsigned long address, struct page *pg);
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extern void copy_user_page(void *to, void *from, unsigned long address, struct page *pg);
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extern void __clear_user_page(void *to, void *orig_to);
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extern void __copy_user_page(void *to, void *from, void *orig_to);
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#elif defined(CONFIG_CPU_SH2) || defined(CONFIG_CPU_SH3) || !defined(CONFIG_MMU)
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#else
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#define clear_user_page(page, vaddr, pg) clear_page(page)
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#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
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#endif
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@ -563,7 +563,8 @@ struct mm_struct;
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extern unsigned int kobjsize(const void *objp);
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#endif /* !CONFIG_MMU */
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#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
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#if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \
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defined(CONFIG_SH7705_CACHE_32KB))
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#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
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extern pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
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#endif
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