forked from luck/tmp_suning_uos_patched
ASoC: sh: fsi: remove runtime register check from fsi_reg_xxx
Current FSI driver was checking register range on fsi_reg_xxx function. This runtime check was added to avoid an illegal access from wrong/mistake implementation. But it is useless check under the correct implementation. This patch escape runtime check by using macro technique. If there is wrong implementation, it will be compile error. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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@ -19,19 +19,19 @@
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#include <sound/soc.h>
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#include <sound/sh_fsi.h>
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#define DO_FMT 0x0000
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#define DOFF_CTL 0x0004
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#define DOFF_ST 0x0008
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#define DI_FMT 0x000C
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#define DIFF_CTL 0x0010
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#define DIFF_ST 0x0014
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#define CKG1 0x0018
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#define CKG2 0x001C
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#define DIDT 0x0020
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#define DODT 0x0024
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#define MUTE_ST 0x0028
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#define OUT_SEL 0x0030
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#define REG_END OUT_SEL
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/* PortA/PortB register */
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#define REG_DO_FMT 0x0000
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#define REG_DOFF_CTL 0x0004
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#define REG_DOFF_ST 0x0008
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#define REG_DI_FMT 0x000C
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#define REG_DIFF_CTL 0x0010
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#define REG_DIFF_ST 0x0014
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#define REG_CKG1 0x0018
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#define REG_CKG2 0x001C
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#define REG_DIDT 0x0020
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#define REG_DODT 0x0024
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#define REG_MUTE_ST 0x0028
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#define REG_OUT_SEL 0x0030
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#define A_MST_CTLR 0x0180
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#define B_MST_CTLR 0x01A0
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@ -191,35 +191,14 @@ static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
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__fsi_reg_write(reg, val);
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}
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static void fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data)
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{
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if (reg > REG_END) {
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pr_err("fsi: register access err (%s)\n", __func__);
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return;
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}
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#define fsi_reg_write(p, r, d)\
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__fsi_reg_write((u32)(p->base + REG_##r), d)
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__fsi_reg_write((u32)(fsi->base + reg), data);
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}
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#define fsi_reg_read(p, r)\
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__fsi_reg_read((u32)(p->base + REG_##r))
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static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg)
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{
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if (reg > REG_END) {
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pr_err("fsi: register access err (%s)\n", __func__);
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return 0;
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}
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return __fsi_reg_read((u32)(fsi->base + reg));
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}
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static void fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data)
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{
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if (reg > REG_END) {
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pr_err("fsi: register access err (%s)\n", __func__);
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return;
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}
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__fsi_reg_mask_set((u32)(fsi->base + reg), mask, data);
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}
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#define fsi_reg_mask_set(p, r, m, d)\
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__fsi_reg_mask_set((u32)(p->base + REG_##r), m, d)
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static u32 fsi_master_read(struct fsi_master *master, u32 reg)
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{
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@ -369,11 +348,13 @@ static void fsi_stream_pop(struct fsi_priv *fsi, int is_play)
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static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play)
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{
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u32 status;
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u32 reg = is_play ? DOFF_ST : DIFF_ST;
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struct fsi_stream *io = fsi_get_stream(fsi, is_play);
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int data_num;
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status = fsi_reg_read(fsi, reg);
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status = is_play ?
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fsi_reg_read(fsi, DOFF_ST) :
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fsi_reg_read(fsi, DIFF_ST);
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data_num = 0x1ff & (status >> 8);
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data_num *= io->chan_num;
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@ -541,7 +522,7 @@ static void fsi_fifo_init(struct fsi_priv *fsi,
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{
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struct fsi_master *master = fsi_get_master(fsi);
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struct fsi_stream *io = fsi_get_stream(fsi, is_play);
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u32 ctrl, shift, i;
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u32 shift, i;
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/* get on-chip RAM capacity */
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shift = fsi_master_read(master, FIFO_SZ);
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@ -574,13 +555,17 @@ static void fsi_fifo_init(struct fsi_priv *fsi,
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dev_dbg(dai->dev, "%d channel %d store\n",
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io->chan_num, io->fifo_max_num);
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ctrl = is_play ? DOFF_CTL : DIFF_CTL;
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/* set interrupt generation factor */
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fsi_reg_write(fsi, ctrl, IRQ_HALF);
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/* clear FIFO */
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fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR);
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/*
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* set interrupt generation factor
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* clear FIFO
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*/
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if (is_play) {
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fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
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fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
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} else {
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fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
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fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
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}
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}
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static void fsi_soft_all_reset(struct fsi_master *master)
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@ -601,7 +586,6 @@ static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int startup, int stream)
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struct snd_pcm_substream *substream = NULL;
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int is_play = fsi_stream_is_play(stream);
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struct fsi_stream *io = fsi_get_stream(fsi, is_play);
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u32 status_reg = is_play ? DOFF_ST : DIFF_ST;
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int data_residue_num;
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int data_num;
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int data_num_max;
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@ -692,14 +676,19 @@ static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int startup, int stream)
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/* check fifo status */
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if (!startup) {
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struct snd_soc_dai *dai = fsi_get_dai(substream);
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u32 status = fsi_reg_read(fsi, status_reg);
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u32 status = is_play ?
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fsi_reg_read(fsi, DOFF_ST) :
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fsi_reg_read(fsi, DIFF_ST);
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if (status & ERR_OVER)
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dev_err(dai->dev, "over run\n");
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if (status & ERR_UNDER)
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dev_err(dai->dev, "under run\n");
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}
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fsi_reg_write(fsi, status_reg, 0);
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is_play ?
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fsi_reg_write(fsi, DOFF_ST, 0) :
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fsi_reg_write(fsi, DIFF_ST, 0);
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/* re-enable irq */
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fsi_irq_enable(fsi, is_play);
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@ -756,7 +745,6 @@ static int fsi_dai_startup(struct snd_pcm_substream *substream,
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struct fsi_stream *io;
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u32 flags = fsi_get_info_flags(fsi);
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u32 fmt;
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u32 reg;
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u32 data;
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int is_play = fsi_is_play(substream);
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int is_master;
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@ -788,7 +776,6 @@ static int fsi_dai_startup(struct snd_pcm_substream *substream,
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/* do fmt, di fmt */
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data = 0;
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reg = is_play ? DO_FMT : DI_FMT;
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fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags);
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switch (fmt) {
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case SH_FSI_FMT_MONO:
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@ -831,7 +818,9 @@ static int fsi_dai_startup(struct snd_pcm_substream *substream,
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dev_err(dai->dev, "unknown format.\n");
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return -EINVAL;
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}
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fsi_reg_write(fsi, reg, data);
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is_play ?
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fsi_reg_write(fsi, DO_FMT, data) :
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fsi_reg_write(fsi, DI_FMT, data);
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/* irq clear */
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fsi_irq_disable(fsi, is_play);
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