forked from luck/tmp_suning_uos_patched
ARM: OMAP4: PM: CPU1 wakeup workaround from Low power modes
The SGI(Software Generated Interrupts) are not wakeup capable from low power states. This is known limitation on OMAP4 and needs to be worked around by using software forced clockdomain wake-up. CPU0 forces the CPU1 clockdomain to software force wakeup. More details can be found in OMAP4430 TRM - Version J Section : 4.3.4.2 Power States of CPU0 and CPU1 Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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@ -28,6 +28,8 @@
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#include "common.h"
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#include "clockdomain.h"
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/* SCU base address */
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static void __iomem *scu_base;
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@ -68,6 +70,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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static struct clockdomain *cpu1_clkdm;
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static bool booted;
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/*
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* Set synchronisation state between this boot processor
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* and the secondary one
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@ -83,6 +87,29 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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omap_modify_auxcoreboot0(0x200, 0xfffffdff);
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flush_cache_all();
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smp_wmb();
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if (!cpu1_clkdm)
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cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
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/*
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* The SGI(Software Generated Interrupts) are not wakeup capable
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* from low power states. This is known limitation on OMAP4 and
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* needs to be worked around by using software forced clockdomain
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* wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
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* software force wakeup. The clockdomain is then put back to
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* hardware supervised mode.
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* More details can be found in OMAP4430 TRM - Version J
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* Section :
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* 4.3.4.2 Power States of CPU0 and CPU1
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*/
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if (booted) {
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clkdm_wakeup(cpu1_clkdm);
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clkdm_allow_idle(cpu1_clkdm);
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} else {
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dsb_sev();
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booted = true;
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}
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gic_raise_softirq(cpumask_of(cpu), 1);
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/*
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