forked from luck/tmp_suning_uos_patched
Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
Pull m68knommu updates from Greg Ungerer: "These changes all relate to converting the IO access functions for the ColdFire (and all other non-MMU m68k) platforms to use asm-generic IO instead. This makes the IO support the same on all ColdFire (regardless of MMU enabled or not) and means we can now support PCI in non-MMU mode. As a bonus these changes remove more code than they add" * 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: m68k: fix ColdFire PCI config reads and writes m68k: introduce iomem() macro for __iomem conversions m68k: allow ColdFire PCI bus on MMU and non-MMU configuration m68k: fix ioremapping for internal ColdFire peripherals m68k: fix read/write multi-byte IO for PCI on ColdFire m68k: don't redefine access functions if we have PCI m68k: remove old ColdFire IO access support code m68k: use io_no.h for MMU and non-MMU enabled ColdFire m68k: setup PCI support code in io_no.h m68k: group io mapping definitions and functions m68k: rework raw access macros for the non-MMU case m68k: use asm-generic/io.h for non-MMU io access functions m68k: put definition guards around virt_to_phys and phys_to_virt m68k: move *_relaxed macros into io_no.h and io_mm.h
This commit is contained in:
Linus Torvalds
commit
eab733afcb
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@ -59,6 +59,10 @@ config ATARI_ROM_ISA
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config GENERIC_ISA_DMA
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def_bool ISA
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source "drivers/zorro/Kconfig"
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endif
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config PCI
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bool "PCI support"
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depends on M54xx
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@ -66,10 +70,8 @@ config PCI
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Enable the PCI bus. Support for the PCI bus hardware built into the
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ColdFire 547x and 548x processors.
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if PCI
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source "drivers/pci/Kconfig"
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source "drivers/zorro/Kconfig"
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endif
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if !MMU
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@ -23,20 +23,10 @@
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/*
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* Memory and IO mappings. We use a 1:1 mapping for local host memory to
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* PCI bus memory (no reason not to really). IO space doesn't matter, we
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* always use access functions for that. The device configuration space is
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* mapped over the IO map space when we enable it in the PCICAR register.
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* PCI bus memory (no reason not to really). IO space is mapped in its own
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* separate address region. The device configuration space is mapped over
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* the IO map space when we enable it in the PCICAR register.
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*/
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#define PCI_MEM_PA 0xf0000000 /* Host physical address */
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#define PCI_MEM_BA 0xf0000000 /* Bus physical address */
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#define PCI_MEM_SIZE 0x08000000 /* 128 MB */
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#define PCI_MEM_MASK (PCI_MEM_SIZE - 1)
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#define PCI_IO_PA 0xf8000000 /* Host physical address */
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#define PCI_IO_BA 0x00000000 /* Bus physical address */
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#define PCI_IO_SIZE 0x00010000 /* 64k */
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#define PCI_IO_MASK (PCI_IO_SIZE - 1)
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static struct pci_bus *rootbus;
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static unsigned long iospace;
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@ -56,13 +46,6 @@ static unsigned char mcf_host_irq[] = {
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0, 69, 69, 71, 71,
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};
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static inline void syncio(void)
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{
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/* The ColdFire "nop" instruction waits for all bus IO to complete */
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__asm__ __volatile__ ("nop");
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}
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/*
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* Configuration space access functions. Configuration space access is
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* through the IO mapping window, enabling it via the PCICAR register.
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@ -84,9 +67,9 @@ static int mcf_pci_readconfig(struct pci_bus *bus, unsigned int devfn,
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return PCIBIOS_SUCCESSFUL;
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}
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syncio();
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addr = mcf_mk_pcicar(bus->number, devfn, where);
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__raw_writel(PCICAR_E | addr, PCICAR);
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__raw_readl(PCICAR);
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addr = iospace + (where & 0x3);
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switch (size) {
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@ -101,8 +84,8 @@ static int mcf_pci_readconfig(struct pci_bus *bus, unsigned int devfn,
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break;
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}
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syncio();
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__raw_writel(0, PCICAR);
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__raw_readl(PCICAR);
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return PCIBIOS_SUCCESSFUL;
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}
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@ -116,9 +99,9 @@ static int mcf_pci_writeconfig(struct pci_bus *bus, unsigned int devfn,
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return PCIBIOS_SUCCESSFUL;
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}
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syncio();
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addr = mcf_mk_pcicar(bus->number, devfn, where);
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__raw_writel(PCICAR_E | addr, PCICAR);
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__raw_readl(PCICAR);
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addr = iospace + (where & 0x3);
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switch (size) {
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@ -133,8 +116,8 @@ static int mcf_pci_writeconfig(struct pci_bus *bus, unsigned int devfn,
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break;
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}
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syncio();
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__raw_writel(0, PCICAR);
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__raw_readl(PCICAR);
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return PCIBIOS_SUCCESSFUL;
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}
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@ -143,89 +126,6 @@ static struct pci_ops mcf_pci_ops = {
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.write = mcf_pci_writeconfig,
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};
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/*
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* IO address space access functions. Pretty strait forward, these are
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* directly mapped in to the IO mapping window. And that is mapped into
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* virtual address space.
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*/
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u8 mcf_pci_inb(u32 addr)
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{
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return __raw_readb(iospace + (addr & PCI_IO_MASK));
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}
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EXPORT_SYMBOL(mcf_pci_inb);
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u16 mcf_pci_inw(u32 addr)
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{
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return le16_to_cpu(__raw_readw(iospace + (addr & PCI_IO_MASK)));
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}
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EXPORT_SYMBOL(mcf_pci_inw);
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u32 mcf_pci_inl(u32 addr)
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{
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return le32_to_cpu(__raw_readl(iospace + (addr & PCI_IO_MASK)));
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}
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EXPORT_SYMBOL(mcf_pci_inl);
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void mcf_pci_insb(u32 addr, u8 *buf, u32 len)
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{
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for (; len; len--)
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*buf++ = mcf_pci_inb(addr);
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}
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EXPORT_SYMBOL(mcf_pci_insb);
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void mcf_pci_insw(u32 addr, u16 *buf, u32 len)
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{
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for (; len; len--)
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*buf++ = mcf_pci_inw(addr);
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}
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EXPORT_SYMBOL(mcf_pci_insw);
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void mcf_pci_insl(u32 addr, u32 *buf, u32 len)
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{
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for (; len; len--)
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*buf++ = mcf_pci_inl(addr);
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}
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EXPORT_SYMBOL(mcf_pci_insl);
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void mcf_pci_outb(u8 v, u32 addr)
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{
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__raw_writeb(v, iospace + (addr & PCI_IO_MASK));
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}
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EXPORT_SYMBOL(mcf_pci_outb);
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void mcf_pci_outw(u16 v, u32 addr)
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{
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__raw_writew(cpu_to_le16(v), iospace + (addr & PCI_IO_MASK));
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}
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EXPORT_SYMBOL(mcf_pci_outw);
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void mcf_pci_outl(u32 v, u32 addr)
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{
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__raw_writel(cpu_to_le32(v), iospace + (addr & PCI_IO_MASK));
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}
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EXPORT_SYMBOL(mcf_pci_outl);
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void mcf_pci_outsb(u32 addr, const u8 *buf, u32 len)
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{
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for (; len; len--)
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mcf_pci_outb(*buf++, addr);
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}
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EXPORT_SYMBOL(mcf_pci_outsb);
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void mcf_pci_outsw(u32 addr, const u16 *buf, u32 len)
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{
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for (; len; len--)
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mcf_pci_outw(*buf++, addr);
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}
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EXPORT_SYMBOL(mcf_pci_outsw);
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void mcf_pci_outsl(u32 addr, const u32 *buf, u32 len)
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{
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for (; len; len--)
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mcf_pci_outl(*buf++, addr);
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}
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EXPORT_SYMBOL(mcf_pci_outsl);
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/*
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* Initialize the PCI bus registers, and scan the bus.
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*/
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@ -23,6 +23,7 @@
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#include <linux/types.h>
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#include <asm/bootinfo-atari.h>
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#include <asm/raw_io.h>
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#include <asm/kmap.h>
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extern u_long atari_mch_cookie;
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extern u_long atari_mch_type;
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@ -1,14 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifdef __uClinux__
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#if defined(__uClinux__) || defined(CONFIG_COLDFIRE)
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#include <asm/io_no.h>
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#else
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#include <asm/io_mm.h>
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#endif
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#define readb_relaxed(addr) readb(addr)
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#define readw_relaxed(addr) readw(addr)
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#define readl_relaxed(addr) readl(addr)
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#define writeb_relaxed(b, addr) writeb(b, addr)
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#define writew_relaxed(b, addr) writew(b, addr)
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#define writel_relaxed(b, addr) writel(b, addr)
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@ -26,6 +26,7 @@
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#include <linux/compiler.h>
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#include <asm/raw_io.h>
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#include <asm/virtconvert.h>
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#include <asm/kmap.h>
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#include <asm-generic/iomap.h>
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@ -85,53 +86,7 @@
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#endif /* ATARI_ROM_ISA */
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#if defined(CONFIG_PCI) && defined(CONFIG_COLDFIRE)
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#define HAVE_ARCH_PIO_SIZE
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#define PIO_OFFSET 0
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#define PIO_MASK 0xffff
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#define PIO_RESERVED 0x10000
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u8 mcf_pci_inb(u32 addr);
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u16 mcf_pci_inw(u32 addr);
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u32 mcf_pci_inl(u32 addr);
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void mcf_pci_insb(u32 addr, u8 *buf, u32 len);
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void mcf_pci_insw(u32 addr, u16 *buf, u32 len);
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void mcf_pci_insl(u32 addr, u32 *buf, u32 len);
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void mcf_pci_outb(u8 v, u32 addr);
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void mcf_pci_outw(u16 v, u32 addr);
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void mcf_pci_outl(u32 v, u32 addr);
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void mcf_pci_outsb(u32 addr, const u8 *buf, u32 len);
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void mcf_pci_outsw(u32 addr, const u16 *buf, u32 len);
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void mcf_pci_outsl(u32 addr, const u32 *buf, u32 len);
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#define inb mcf_pci_inb
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#define inb_p mcf_pci_inb
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#define inw mcf_pci_inw
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#define inw_p mcf_pci_inw
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#define inl mcf_pci_inl
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#define inl_p mcf_pci_inl
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#define insb mcf_pci_insb
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#define insw mcf_pci_insw
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#define insl mcf_pci_insl
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#define outb mcf_pci_outb
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#define outb_p mcf_pci_outb
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#define outw mcf_pci_outw
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#define outw_p mcf_pci_outw
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#define outl mcf_pci_outl
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#define outl_p mcf_pci_outl
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#define outsb mcf_pci_outsb
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#define outsw mcf_pci_outsw
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#define outsl mcf_pci_outsl
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#define readb(addr) in_8(addr)
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#define writeb(v, addr) out_8((addr), (v))
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#define readw(addr) in_le16(addr)
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#define writew(v, addr) out_le16((addr), (v))
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#elif defined(CONFIG_ISA) || defined(CONFIG_ATARI_ROM_ISA)
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#if defined(CONFIG_ISA) || defined(CONFIG_ATARI_ROM_ISA)
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#if MULTI_ISA == 0
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#undef MULTI_ISA
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|
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@ -414,8 +369,7 @@ static inline void isa_delay(void)
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#define writew(val, addr) out_le16((addr), (val))
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#endif /* CONFIG_ATARI_ROM_ISA */
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#if !defined(CONFIG_ISA) && !defined(CONFIG_ATARI_ROM_ISA) && \
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!(defined(CONFIG_PCI) && defined(CONFIG_COLDFIRE))
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#if !defined(CONFIG_ISA) && !defined(CONFIG_ATARI_ROM_ISA)
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/*
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* We need to define dummy functions for GENERIC_IOMAP support.
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*/
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@ -461,39 +415,6 @@ static inline void isa_delay(void)
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#define mmiowb()
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static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
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{
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return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
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}
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static inline void __iomem *ioremap_nocache(unsigned long physaddr, unsigned long size)
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{
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return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
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}
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#define ioremap_uc ioremap_nocache
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static inline void __iomem *ioremap_wt(unsigned long physaddr,
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unsigned long size)
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{
|
||||
return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
|
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}
|
||||
static inline void __iomem *ioremap_fullcache(unsigned long physaddr,
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unsigned long size)
|
||||
{
|
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return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
|
||||
}
|
||||
|
||||
static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
|
||||
{
|
||||
__builtin_memset((void __force *) addr, val, count);
|
||||
}
|
||||
static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
|
||||
{
|
||||
__builtin_memcpy(dst, (void __force *) src, count);
|
||||
}
|
||||
static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
|
||||
{
|
||||
__builtin_memcpy((void __force *) dst, src, count);
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SUN3
|
||||
#define IO_SPACE_LIMIT 0xffff
|
||||
#else
|
||||
|
|
@ -515,13 +436,12 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
|
|||
*/
|
||||
#define xlate_dev_kmem_ptr(p) p
|
||||
|
||||
static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
|
||||
{
|
||||
return (void __iomem *) port;
|
||||
}
|
||||
#define readb_relaxed(addr) readb(addr)
|
||||
#define readw_relaxed(addr) readw(addr)
|
||||
#define readl_relaxed(addr) readl(addr)
|
||||
|
||||
static inline void ioport_unmap(void __iomem *p)
|
||||
{
|
||||
}
|
||||
#define writeb_relaxed(b, addr) writeb(b, addr)
|
||||
#define writew_relaxed(b, addr) writew(b, addr)
|
||||
#define writel_relaxed(b, addr) writel(b, addr)
|
||||
|
||||
#endif /* _IO_H */
|
||||
|
|
|
|||
|
|
@ -2,191 +2,148 @@
|
|||
#ifndef _M68KNOMMU_IO_H
|
||||
#define _M68KNOMMU_IO_H
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#define ARCH_HAS_IOREMAP_WT
|
||||
|
||||
#include <asm/virtconvert.h>
|
||||
#include <asm-generic/iomap.h>
|
||||
/*
|
||||
* Convert a physical memory address into a IO memory address.
|
||||
* For us this is trivially a type cast.
|
||||
*/
|
||||
#define iomem(a) ((void __iomem *) (a))
|
||||
|
||||
/*
|
||||
* These are for ISA/PCI shared memory _only_ and should never be used
|
||||
* on any other type of memory, including Zorro memory. They are meant to
|
||||
* access the bus in the bus byte order which is little-endian!.
|
||||
*
|
||||
* readX/writeX() are used to access memory mapped devices. On some
|
||||
* architectures the memory mapped IO stuff needs to be accessed
|
||||
* differently. On the m68k architecture, we just read/write the
|
||||
* memory location directly.
|
||||
* The non-MMU m68k and ColdFire IO and memory mapped hardware access
|
||||
* functions have always worked in CPU native endian. We need to define
|
||||
* that behavior here first before we include asm-generic/io.h.
|
||||
*/
|
||||
/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
|
||||
* two accesses to memory, which may be undesirable for some devices.
|
||||
*/
|
||||
|
||||
/*
|
||||
* swap functions are sometimes needed to interface little-endian hardware
|
||||
*/
|
||||
static inline unsigned short _swapw(volatile unsigned short v)
|
||||
{
|
||||
return ((v << 8) | (v >> 8));
|
||||
}
|
||||
|
||||
static inline unsigned int _swapl(volatile unsigned long v)
|
||||
{
|
||||
return ((v << 24) | ((v & 0xff00) << 8) | ((v & 0xff0000) >> 8) | (v >> 24));
|
||||
}
|
||||
|
||||
#define readb(addr) \
|
||||
#define __raw_readb(addr) \
|
||||
({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
|
||||
#define readw(addr) \
|
||||
#define __raw_readw(addr) \
|
||||
({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
|
||||
#define readl(addr) \
|
||||
#define __raw_readl(addr) \
|
||||
({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
|
||||
|
||||
#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
|
||||
#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
|
||||
#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
|
||||
#define __raw_writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
|
||||
#define __raw_writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
|
||||
#define __raw_writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
|
||||
|
||||
#define __raw_readb readb
|
||||
#define __raw_readw readw
|
||||
#define __raw_readl readl
|
||||
#define __raw_writeb writeb
|
||||
#define __raw_writew writew
|
||||
#define __raw_writel writel
|
||||
#if defined(CONFIG_COLDFIRE)
|
||||
/*
|
||||
* For ColdFire platforms we may need to do some extra checks for what
|
||||
* type of address range we are accessing. Include the ColdFire platform
|
||||
* definitions so we can figure out if need to do something special.
|
||||
*/
|
||||
#include <asm/byteorder.h>
|
||||
#include <asm/coldfire.h>
|
||||
#include <asm/mcfsim.h>
|
||||
#endif /* CONFIG_COLDFIRE */
|
||||
|
||||
static inline void io_outsb(unsigned int addr, const void *buf, int len)
|
||||
#if defined(IOMEMBASE)
|
||||
/*
|
||||
* The ColdFire SoC internal peripherals are mapped into virtual address
|
||||
* space using the ACR registers of the cache control unit. This means we
|
||||
* are using a 1:1 physical:virtual mapping for them. We can quickly
|
||||
* determine if we are accessing an internal peripheral device given the
|
||||
* physical or vitrual address using the same range check. This check logic
|
||||
* applies just the same of there is no MMU but something like a PCI bus
|
||||
* is present.
|
||||
*/
|
||||
static int __cf_internalio(unsigned long addr)
|
||||
{
|
||||
volatile unsigned char *ap = (volatile unsigned char *) addr;
|
||||
unsigned char *bp = (unsigned char *) buf;
|
||||
while (len--)
|
||||
*ap = *bp++;
|
||||
return (addr >= IOMEMBASE) && (addr <= IOMEMBASE + IOMEMSIZE - 1);
|
||||
}
|
||||
|
||||
static inline void io_outsw(unsigned int addr, const void *buf, int len)
|
||||
static int cf_internalio(const volatile void __iomem *addr)
|
||||
{
|
||||
volatile unsigned short *ap = (volatile unsigned short *) addr;
|
||||
unsigned short *bp = (unsigned short *) buf;
|
||||
while (len--)
|
||||
*ap = _swapw(*bp++);
|
||||
return __cf_internalio((unsigned long) addr);
|
||||
}
|
||||
|
||||
static inline void io_outsl(unsigned int addr, const void *buf, int len)
|
||||
{
|
||||
volatile unsigned int *ap = (volatile unsigned int *) addr;
|
||||
unsigned int *bp = (unsigned int *) buf;
|
||||
while (len--)
|
||||
*ap = _swapl(*bp++);
|
||||
}
|
||||
|
||||
static inline void io_insb(unsigned int addr, void *buf, int len)
|
||||
{
|
||||
volatile unsigned char *ap = (volatile unsigned char *) addr;
|
||||
unsigned char *bp = (unsigned char *) buf;
|
||||
while (len--)
|
||||
*bp++ = *ap;
|
||||
}
|
||||
|
||||
static inline void io_insw(unsigned int addr, void *buf, int len)
|
||||
{
|
||||
volatile unsigned short *ap = (volatile unsigned short *) addr;
|
||||
unsigned short *bp = (unsigned short *) buf;
|
||||
while (len--)
|
||||
*bp++ = _swapw(*ap);
|
||||
}
|
||||
|
||||
static inline void io_insl(unsigned int addr, void *buf, int len)
|
||||
{
|
||||
volatile unsigned int *ap = (volatile unsigned int *) addr;
|
||||
unsigned int *bp = (unsigned int *) buf;
|
||||
while (len--)
|
||||
*bp++ = _swapl(*ap);
|
||||
}
|
||||
|
||||
#define mmiowb()
|
||||
|
||||
/*
|
||||
* make the short names macros so specific devices
|
||||
* can override them as required
|
||||
* We need to treat built-in peripherals and bus based address ranges
|
||||
* differently. Local built-in peripherals (and the ColdFire SoC parts
|
||||
* have quite a lot of them) are always native endian - which is big
|
||||
* endian on m68k/ColdFire. Bus based address ranges, like the PCI bus,
|
||||
* are accessed little endian - so we need to byte swap those.
|
||||
*/
|
||||
|
||||
#define memset_io(a,b,c) memset((void *)(a),(b),(c))
|
||||
#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
|
||||
#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
|
||||
|
||||
#define inb(addr) readb(addr)
|
||||
#define inw(addr) readw(addr)
|
||||
#define inl(addr) readl(addr)
|
||||
#define outb(x,addr) ((void) writeb(x,addr))
|
||||
#define outw(x,addr) ((void) writew(x,addr))
|
||||
#define outl(x,addr) ((void) writel(x,addr))
|
||||
|
||||
#define inb_p(addr) inb(addr)
|
||||
#define inw_p(addr) inw(addr)
|
||||
#define inl_p(addr) inl(addr)
|
||||
#define outb_p(x,addr) outb(x,addr)
|
||||
#define outw_p(x,addr) outw(x,addr)
|
||||
#define outl_p(x,addr) outl(x,addr)
|
||||
|
||||
#define outsb(a,b,l) io_outsb(a,b,l)
|
||||
#define outsw(a,b,l) io_outsw(a,b,l)
|
||||
#define outsl(a,b,l) io_outsl(a,b,l)
|
||||
|
||||
#define insb(a,b,l) io_insb(a,b,l)
|
||||
#define insw(a,b,l) io_insw(a,b,l)
|
||||
#define insl(a,b,l) io_insl(a,b,l)
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
|
||||
/* Values for nocacheflag and cmode */
|
||||
#define IOMAP_FULL_CACHING 0
|
||||
#define IOMAP_NOCACHE_SER 1
|
||||
#define IOMAP_NOCACHE_NONSER 2
|
||||
#define IOMAP_WRITETHROUGH 3
|
||||
|
||||
static inline void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag)
|
||||
#define readw readw
|
||||
static inline u16 readw(const volatile void __iomem *addr)
|
||||
{
|
||||
return (void *) physaddr;
|
||||
}
|
||||
static inline void *ioremap(unsigned long physaddr, unsigned long size)
|
||||
{
|
||||
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
|
||||
}
|
||||
static inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
|
||||
{
|
||||
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
|
||||
}
|
||||
static inline void *ioremap_wt(unsigned long physaddr, unsigned long size)
|
||||
{
|
||||
return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
|
||||
}
|
||||
static inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size)
|
||||
{
|
||||
return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
|
||||
if (cf_internalio(addr))
|
||||
return __raw_readw(addr);
|
||||
return __le16_to_cpu(__raw_readw(addr));
|
||||
}
|
||||
|
||||
#define iounmap(addr) do { } while(0)
|
||||
#define readl readl
|
||||
static inline u32 readl(const volatile void __iomem *addr)
|
||||
{
|
||||
if (cf_internalio(addr))
|
||||
return __raw_readl(addr);
|
||||
return __le32_to_cpu(__raw_readl(addr));
|
||||
}
|
||||
|
||||
#define writew writew
|
||||
static inline void writew(u16 value, volatile void __iomem *addr)
|
||||
{
|
||||
if (cf_internalio(addr))
|
||||
__raw_writew(value, addr);
|
||||
else
|
||||
__raw_writew(__cpu_to_le16(value), addr);
|
||||
}
|
||||
|
||||
#define writel writel
|
||||
static inline void writel(u32 value, volatile void __iomem *addr)
|
||||
{
|
||||
if (cf_internalio(addr))
|
||||
__raw_writel(value, addr);
|
||||
else
|
||||
__raw_writel(__cpu_to_le32(value), addr);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define readb __raw_readb
|
||||
#define readw __raw_readw
|
||||
#define readl __raw_readl
|
||||
#define writeb __raw_writeb
|
||||
#define writew __raw_writew
|
||||
#define writel __raw_writel
|
||||
|
||||
#endif /* IOMEMBASE */
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
/*
|
||||
* Support for PCI bus access uses the asm-generic access functions.
|
||||
* We need to supply the base address and masks for the normal memory
|
||||
* and IO address space mappings.
|
||||
*/
|
||||
#define PCI_MEM_PA 0xf0000000 /* Host physical address */
|
||||
#define PCI_MEM_BA 0xf0000000 /* Bus physical address */
|
||||
#define PCI_MEM_SIZE 0x08000000 /* 128 MB */
|
||||
#define PCI_MEM_MASK (PCI_MEM_SIZE - 1)
|
||||
|
||||
#define PCI_IO_PA 0xf8000000 /* Host physical address */
|
||||
#define PCI_IO_BA 0x00000000 /* Bus physical address */
|
||||
#define PCI_IO_SIZE 0x00010000 /* 64k */
|
||||
#define PCI_IO_MASK (PCI_IO_SIZE - 1)
|
||||
|
||||
#define HAVE_ARCH_PIO_SIZE
|
||||
#define PIO_OFFSET 0
|
||||
#define PIO_MASK 0xffff
|
||||
#define PIO_RESERVED 0x10000
|
||||
#define PCI_IOBASE ((void __iomem *) PCI_IO_PA)
|
||||
#define PCI_SPACE_LIMIT PCI_IO_MASK
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
/*
|
||||
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
|
||||
* access
|
||||
* These are defined in kmap.h as static inline functions. To maintain
|
||||
* previous behavior we put these define guards here so io_mm.h doesn't
|
||||
* see them.
|
||||
*/
|
||||
#define xlate_dev_mem_ptr(p) __va(p)
|
||||
#ifdef CONFIG_MMU
|
||||
#define memset_io memset_io
|
||||
#define memcpy_fromio memcpy_fromio
|
||||
#define memcpy_toio memcpy_toio
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Convert a virtual cached pointer to an uncached pointer
|
||||
*/
|
||||
#define xlate_dev_kmem_ptr(p) p
|
||||
|
||||
static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
|
||||
{
|
||||
return (void __iomem *) port;
|
||||
}
|
||||
|
||||
static inline void ioport_unmap(void __iomem *p)
|
||||
{
|
||||
}
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#include <asm/kmap.h>
|
||||
#include <asm/virtconvert.h>
|
||||
#include <asm-generic/io.h>
|
||||
|
||||
#endif /* _M68KNOMMU_IO_H */
|
||||
|
|
|
|||
80
arch/m68k/include/asm/kmap.h
Normal file
80
arch/m68k/include/asm/kmap.h
Normal file
|
|
@ -0,0 +1,80 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _KMAP_H
|
||||
#define _KMAP_H
|
||||
|
||||
#ifdef CONFIG_MMU
|
||||
|
||||
/* Values for nocacheflag and cmode */
|
||||
#define IOMAP_FULL_CACHING 0
|
||||
#define IOMAP_NOCACHE_SER 1
|
||||
#define IOMAP_NOCACHE_NONSER 2
|
||||
#define IOMAP_WRITETHROUGH 3
|
||||
|
||||
/*
|
||||
* These functions exported by arch/m68k/mm/kmap.c.
|
||||
* Only needed on MMU enabled systems.
|
||||
*/
|
||||
extern void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
|
||||
int cacheflag);
|
||||
extern void iounmap(void __iomem *addr);
|
||||
extern void __iounmap(void *addr, unsigned long size);
|
||||
|
||||
#define ioremap ioremap
|
||||
static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
|
||||
{
|
||||
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
|
||||
}
|
||||
|
||||
#define ioremap_nocache ioremap_nocache
|
||||
static inline void __iomem *ioremap_nocache(unsigned long physaddr,
|
||||
unsigned long size)
|
||||
{
|
||||
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
|
||||
}
|
||||
|
||||
#define ioremap_uc ioremap_nocache
|
||||
static inline void __iomem *ioremap_wt(unsigned long physaddr,
|
||||
unsigned long size)
|
||||
{
|
||||
return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
|
||||
}
|
||||
|
||||
#define ioremap_fillcache ioremap_fullcache
|
||||
static inline void __iomem *ioremap_fullcache(unsigned long physaddr,
|
||||
unsigned long size)
|
||||
{
|
||||
return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
|
||||
}
|
||||
|
||||
static inline void memset_io(volatile void __iomem *addr, unsigned char val,
|
||||
int count)
|
||||
{
|
||||
__builtin_memset((void __force *) addr, val, count);
|
||||
}
|
||||
|
||||
static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
|
||||
int count)
|
||||
{
|
||||
__builtin_memcpy(dst, (void __force *) src, count);
|
||||
}
|
||||
|
||||
static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
|
||||
int count)
|
||||
{
|
||||
__builtin_memcpy((void __force *) dst, src, count);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_MMU */
|
||||
|
||||
#define ioport_map ioport_map
|
||||
static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
|
||||
{
|
||||
return (void __iomem *) port;
|
||||
}
|
||||
|
||||
#define ioport_unmap ioport_unmap
|
||||
static inline void ioport_unmap(void __iomem *p)
|
||||
{
|
||||
}
|
||||
|
||||
#endif /* _KMAP_H */
|
||||
|
|
@ -3,6 +3,7 @@
|
|||
#define _ASM_M68K_NUBUS_H
|
||||
|
||||
#include <asm/raw_io.h>
|
||||
#include <asm/kmap.h>
|
||||
|
||||
#define nubus_readb raw_inb
|
||||
#define nubus_readw raw_inw
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#define _Q40_MASTER_H
|
||||
|
||||
#include <asm/raw_io.h>
|
||||
|
||||
#include <asm/kmap.h>
|
||||
|
||||
#define q40_master_addr 0xff000000
|
||||
|
||||
|
|
|
|||
|
|
@ -13,20 +13,6 @@
|
|||
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
|
||||
/* Values for nocacheflag and cmode */
|
||||
#define IOMAP_FULL_CACHING 0
|
||||
#define IOMAP_NOCACHE_SER 1
|
||||
#define IOMAP_NOCACHE_NONSER 2
|
||||
#define IOMAP_WRITETHROUGH 3
|
||||
|
||||
extern void iounmap(void __iomem *addr);
|
||||
|
||||
extern void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
|
||||
int cacheflag);
|
||||
extern void __iounmap(void *addr, unsigned long size);
|
||||
|
||||
|
||||
/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
|
||||
* two accesses to memory, which may be undesirable for some devices.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,7 +2,15 @@
|
|||
#ifndef _ASM_M68K_VGA_H
|
||||
#define _ASM_M68K_VGA_H
|
||||
|
||||
/*
|
||||
* Some ColdFire platforms do in fact have a PCI bus. So for those we want
|
||||
* to use the real IO access functions, don't fake them out or redirect them
|
||||
* for that case.
|
||||
*/
|
||||
#ifndef CONFIG_PCI
|
||||
|
||||
#include <asm/raw_io.h>
|
||||
#include <asm/kmap.h>
|
||||
|
||||
/*
|
||||
* FIXME
|
||||
|
|
@ -25,4 +33,5 @@
|
|||
#define writeb raw_outb
|
||||
#define writew raw_outw
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
#endif /* _ASM_M68K_VGA_H */
|
||||
|
|
|
|||
|
|
@ -16,11 +16,13 @@
|
|||
/*
|
||||
* Change virtual addresses to physical addresses and vv.
|
||||
*/
|
||||
#define virt_to_phys virt_to_phys
|
||||
static inline unsigned long virt_to_phys(void *address)
|
||||
{
|
||||
return __pa(address);
|
||||
}
|
||||
|
||||
#define phys_to_virt phys_to_virt
|
||||
static inline void *phys_to_virt(unsigned long address)
|
||||
{
|
||||
return __va(address);
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
#define _ASM_M68K_ZORRO_H
|
||||
|
||||
#include <asm/raw_io.h>
|
||||
#include <asm/kmap.h>
|
||||
|
||||
#define z_readb raw_inb
|
||||
#define z_readw raw_inw
|
||||
|
|
|
|||
|
|
@ -126,6 +126,10 @@ void __iomem *__ioremap(unsigned long physaddr, unsigned long size, int cachefla
|
|||
return (void __iomem *)physaddr;
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_COLDFIRE
|
||||
if (__cf_internalio(physaddr))
|
||||
return (void __iomem *) physaddr;
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG
|
||||
printk("ioremap: 0x%lx,0x%lx(%d) - ", physaddr, size, cacheflag);
|
||||
|
|
@ -236,6 +240,10 @@ void iounmap(void __iomem *addr)
|
|||
((unsigned long)addr > 0x60000000)))
|
||||
free_io_area((__force void *)addr);
|
||||
#else
|
||||
#ifdef CONFIG_COLDFIRE
|
||||
if (cf_internalio(addr))
|
||||
return;
|
||||
#endif
|
||||
free_io_area((__force void *)addr);
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user