forked from luck/tmp_suning_uos_patched
ASoC: rockchip: i2s: separate capture and playback
If we only clear the tx/rx state when both are disabled it is not possible to start/stop one multiple times while the other is running. Since the two are independently controlled, treat them as such and remove the false dependency between capture and playback. Signed-off-by: John Keeping <john@metanate.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -82,8 +82,8 @@ static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
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I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
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regmap_update_bits(i2s->regmap, I2S_XFER,
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I2S_XFER_TXS_START | I2S_XFER_RXS_START,
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I2S_XFER_TXS_START | I2S_XFER_RXS_START);
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I2S_XFER_TXS_START,
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I2S_XFER_TXS_START);
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i2s->tx_start = true;
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} else {
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@ -92,27 +92,23 @@ static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
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regmap_update_bits(i2s->regmap, I2S_DMACR,
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I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
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if (!i2s->rx_start) {
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regmap_update_bits(i2s->regmap, I2S_XFER,
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I2S_XFER_TXS_START |
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I2S_XFER_RXS_START,
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I2S_XFER_TXS_STOP |
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I2S_XFER_RXS_STOP);
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regmap_update_bits(i2s->regmap, I2S_XFER,
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I2S_XFER_TXS_START,
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I2S_XFER_TXS_STOP);
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regmap_update_bits(i2s->regmap, I2S_CLR,
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I2S_CLR_TXC | I2S_CLR_RXC,
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I2S_CLR_TXC | I2S_CLR_RXC);
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regmap_update_bits(i2s->regmap, I2S_CLR,
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I2S_CLR_TXC,
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I2S_CLR_TXC);
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regmap_read(i2s->regmap, I2S_CLR, &val);
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/* Should wait for clear operation to finish */
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while (val & I2S_CLR_TXC) {
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regmap_read(i2s->regmap, I2S_CLR, &val);
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/* Should wait for clear operation to finish */
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while (val) {
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regmap_read(i2s->regmap, I2S_CLR, &val);
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retry--;
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if (!retry) {
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dev_warn(i2s->dev, "fail to clear\n");
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break;
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}
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retry--;
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if (!retry) {
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dev_warn(i2s->dev, "fail to clear\n");
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break;
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}
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}
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}
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@ -128,8 +124,8 @@ static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
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I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
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regmap_update_bits(i2s->regmap, I2S_XFER,
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I2S_XFER_TXS_START | I2S_XFER_RXS_START,
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I2S_XFER_TXS_START | I2S_XFER_RXS_START);
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I2S_XFER_RXS_START,
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I2S_XFER_RXS_START);
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i2s->rx_start = true;
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} else {
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@ -138,27 +134,23 @@ static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
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regmap_update_bits(i2s->regmap, I2S_DMACR,
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I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
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if (!i2s->tx_start) {
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regmap_update_bits(i2s->regmap, I2S_XFER,
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I2S_XFER_TXS_START |
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I2S_XFER_RXS_START,
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I2S_XFER_TXS_STOP |
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I2S_XFER_RXS_STOP);
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regmap_update_bits(i2s->regmap, I2S_XFER,
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I2S_XFER_RXS_START,
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I2S_XFER_RXS_STOP);
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regmap_update_bits(i2s->regmap, I2S_CLR,
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I2S_CLR_TXC | I2S_CLR_RXC,
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I2S_CLR_TXC | I2S_CLR_RXC);
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regmap_update_bits(i2s->regmap, I2S_CLR,
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I2S_CLR_RXC,
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I2S_CLR_RXC);
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regmap_read(i2s->regmap, I2S_CLR, &val);
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/* Should wait for clear operation to finish */
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while (val & I2S_CLR_RXC) {
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regmap_read(i2s->regmap, I2S_CLR, &val);
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/* Should wait for clear operation to finish */
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while (val) {
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regmap_read(i2s->regmap, I2S_CLR, &val);
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retry--;
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if (!retry) {
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dev_warn(i2s->dev, "fail to clear\n");
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break;
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}
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retry--;
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if (!retry) {
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dev_warn(i2s->dev, "fail to clear\n");
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break;
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}
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}
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}
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