forked from luck/tmp_suning_uos_patched
[media] DRX-K: Tons of coding-style fixes
Tons of coding-style fixes Signed-off-by: Oliver Endriss <o.endriss@gmx.de> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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@ -52,7 +52,7 @@ enum OperationMode {
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OM_DVBT
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};
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typedef enum {
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enum DRXPowerMode {
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DRX_POWER_UP = 0,
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DRX_POWER_MODE_1,
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DRX_POWER_MODE_2,
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@ -72,7 +72,7 @@ typedef enum {
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DRX_POWER_MODE_15,
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DRX_POWER_MODE_16,
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DRX_POWER_DOWN = 255
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}DRXPowerMode_t, *pDRXPowerMode_t;
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};
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/** /brief Intermediate power mode for DRXK, power down OFDM clock domain */
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@ -164,8 +164,7 @@ struct DRXKCfgDvbtEchoThres_t {
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enum DRXFftmode_t fftMode;
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} ;
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struct SCfgAgc
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{
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struct SCfgAgc {
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enum AGC_CTRL_MODE ctrlMode; /* off, user, auto */
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u16 outputLevel; /* range dependent on AGC */
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u16 minOutputLevel; /* range dependent on AGC */
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@ -173,19 +172,17 @@ struct SCfgAgc
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u16 speed; /* range dependent on AGC */
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u16 top; /* rf-agc take over point */
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u16 cutOffCurrent; /* rf-agc is accelerated if output current
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is below cut-off current */
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is below cut-off current */
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u16 IngainTgtMax;
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u16 FastClipCtrlDelay;
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};
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struct SCfgPreSaw
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{
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struct SCfgPreSaw {
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u16 reference; /* pre SAW reference value, range 0 .. 31 */
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bool usePreSaw; /* TRUE algorithms must use pre SAW sense */
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};
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struct DRXKOfdmScCmd_t
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{
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struct DRXKOfdmScCmd_t {
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u16 cmd; /**< Command number */
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u16 subcmd; /**< Sub-command parameter*/
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u16 param0; /**< General purpous param */
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@ -208,127 +205,127 @@ struct drxk_state {
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struct mutex mutex;
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struct mutex ctlock;
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u32 m_Instance; ///< Channel 1,2,3 or 4
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u32 m_Instance; /**< Channel 1,2,3 or 4 */
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int m_ChunkSize;
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int m_ChunkSize;
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u8 Chunk[256];
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bool m_hasLNA;
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bool m_hasDVBT;
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bool m_hasDVBC;
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bool m_hasAudio;
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bool m_hasATV;
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bool m_hasOOB;
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bool m_hasSAWSW; /**< TRUE if mat_tx is available */
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bool m_hasGPIO1; /**< TRUE if mat_rx is available */
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bool m_hasGPIO2; /**< TRUE if GPIO is available */
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bool m_hasIRQN; /**< TRUE if IRQN is available */
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u16 m_oscClockFreq;
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u16 m_HICfgTimingDiv;
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u16 m_HICfgBridgeDelay;
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u16 m_HICfgWakeUpKey;
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u16 m_HICfgTimeout;
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u16 m_HICfgCtrl;
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s32 m_sysClockFreq ; ///< system clock frequency in kHz
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bool m_hasLNA;
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bool m_hasDVBT;
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bool m_hasDVBC;
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bool m_hasAudio;
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bool m_hasATV;
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bool m_hasOOB;
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bool m_hasSAWSW; /**< TRUE if mat_tx is available */
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bool m_hasGPIO1; /**< TRUE if mat_rx is available */
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bool m_hasGPIO2; /**< TRUE if GPIO is available */
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bool m_hasIRQN; /**< TRUE if IRQN is available */
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u16 m_oscClockFreq;
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u16 m_HICfgTimingDiv;
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u16 m_HICfgBridgeDelay;
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u16 m_HICfgWakeUpKey;
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u16 m_HICfgTimeout;
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u16 m_HICfgCtrl;
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s32 m_sysClockFreq; /**< system clock frequency in kHz */
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enum EDrxkState m_DrxkState; ///< State of Drxk (init,stopped,started)
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enum OperationMode m_OperationMode; ///< digital standards
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struct SCfgAgc m_vsbRfAgcCfg; ///< settings for VSB RF-AGC
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struct SCfgAgc m_vsbIfAgcCfg; ///< settings for VSB IF-AGC
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u16 m_vsbPgaCfg; ///< settings for VSB PGA
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struct SCfgPreSaw m_vsbPreSawCfg; ///< settings for pre SAW sense
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s32 m_Quality83percent; ///< MER level (*0.1 dB) for 83% quality indication
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s32 m_Quality93percent; ///< MER level (*0.1 dB) for 93% quality indication
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bool m_smartAntInverted;
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bool m_bDebugEnableBridge;
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bool m_bPDownOpenBridge; ///< only open DRXK bridge before power-down once it has been accessed
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bool m_bPowerDown; ///< Power down when not used
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enum EDrxkState m_DrxkState; /**< State of Drxk (init,stopped,started) */
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enum OperationMode m_OperationMode; /**< digital standards */
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struct SCfgAgc m_vsbRfAgcCfg; /**< settings for VSB RF-AGC */
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struct SCfgAgc m_vsbIfAgcCfg; /**< settings for VSB IF-AGC */
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u16 m_vsbPgaCfg; /**< settings for VSB PGA */
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struct SCfgPreSaw m_vsbPreSawCfg; /**< settings for pre SAW sense */
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s32 m_Quality83percent; /**< MER level (*0.1 dB) for 83% quality indication */
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s32 m_Quality93percent; /**< MER level (*0.1 dB) for 93% quality indication */
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bool m_smartAntInverted;
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bool m_bDebugEnableBridge;
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bool m_bPDownOpenBridge; /**< only open DRXK bridge before power-down once it has been accessed */
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bool m_bPowerDown; /**< Power down when not used */
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u32 m_IqmFsRateOfs; ///< frequency shift as written to DRXK register (28bit fixpoint)
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u32 m_IqmFsRateOfs; /**< frequency shift as written to DRXK register (28bit fixpoint) */
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bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */
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bool m_insertRSByte; /**< If TRUE, insert RS byte */
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bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */
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bool m_invertDATA; /**< If TRUE, invert DATA signals */
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bool m_invertERR; /**< If TRUE, invert ERR signal */
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bool m_invertSTR; /**< If TRUE, invert STR signals */
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bool m_invertVAL; /**< If TRUE, invert VAL signals */
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bool m_invertCLK; /**< If TRUE, invert CLK signals */
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bool m_DVBCStaticCLK;
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bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will
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be used, otherwise clockrate will
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adapt to the bitrate of the TS */
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u32 m_DVBTBitrate;
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u32 m_DVBCBitrate;
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bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */
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bool m_insertRSByte; /**< If TRUE, insert RS byte */
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bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */
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bool m_invertDATA; /**< If TRUE, invert DATA signals */
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bool m_invertERR; /**< If TRUE, invert ERR signal */
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bool m_invertSTR; /**< If TRUE, invert STR signals */
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bool m_invertVAL; /**< If TRUE, invert VAL signals */
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bool m_invertCLK; /**< If TRUE, invert CLK signals */
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bool m_DVBCStaticCLK;
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bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will
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be used, otherwise clockrate will
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adapt to the bitrate of the TS */
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u32 m_DVBTBitrate;
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u32 m_DVBCBitrate;
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u8 m_TSDataStrength;
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u8 m_TSClockkStrength;
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u8 m_TSDataStrength;
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u8 m_TSClockkStrength;
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enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width**/
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u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case
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static clockrate is selected */
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enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width */
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u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case
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static clockrate is selected */
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//LARGE_INTEGER m_StartTime; ///< Contains the time of the last demod start
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s32 m_MpegLockTimeOut; ///< WaitForLockStatus Timeout (counts from start time)
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s32 m_DemodLockTimeOut; ///< WaitForLockStatus Timeout (counts from start time)
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/* LARGE_INTEGER m_StartTime; */ /**< Contains the time of the last demod start */
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s32 m_MpegLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */
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s32 m_DemodLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */
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bool m_disableTEIhandling;
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bool m_disableTEIhandling;
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bool m_RfAgcPol;
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bool m_IfAgcPol;
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bool m_RfAgcPol;
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bool m_IfAgcPol;
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struct SCfgAgc m_atvRfAgcCfg; ///< settings for ATV RF-AGC
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struct SCfgAgc m_atvIfAgcCfg; ///< settings for ATV IF-AGC
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struct SCfgPreSaw m_atvPreSawCfg; ///< settings for ATV pre SAW sense
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bool m_phaseCorrectionBypass;
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s16 m_atvTopVidPeak;
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u16 m_atvTopNoiseTh;
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struct SCfgAgc m_atvRfAgcCfg; /**< settings for ATV RF-AGC */
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struct SCfgAgc m_atvIfAgcCfg; /**< settings for ATV IF-AGC */
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struct SCfgPreSaw m_atvPreSawCfg; /**< settings for ATV pre SAW sense */
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bool m_phaseCorrectionBypass;
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s16 m_atvTopVidPeak;
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u16 m_atvTopNoiseTh;
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enum EDrxkSifAttenuation m_sifAttenuation;
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bool m_enableCVBSOutput;
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bool m_enableSIFOutput;
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bool m_bMirrorFreqSpect;
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enum EDrxkConstellation m_Constellation; ///< Constellation type of the channel
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u32 m_CurrSymbolRate; ///< Current QAM symbol rate
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struct SCfgAgc m_qamRfAgcCfg; ///< settings for QAM RF-AGC
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struct SCfgAgc m_qamIfAgcCfg; ///< settings for QAM IF-AGC
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u16 m_qamPgaCfg; ///< settings for QAM PGA
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struct SCfgPreSaw m_qamPreSawCfg; ///< settings for QAM pre SAW sense
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enum EDrxkInterleaveMode m_qamInterleaveMode; ///< QAM Interleave mode
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u16 m_fecRsPlen;
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u16 m_fecRsPrescale;
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bool m_enableCVBSOutput;
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bool m_enableSIFOutput;
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bool m_bMirrorFreqSpect;
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enum EDrxkConstellation m_Constellation; /**< Constellation type of the channel */
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u32 m_CurrSymbolRate; /**< Current QAM symbol rate */
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struct SCfgAgc m_qamRfAgcCfg; /**< settings for QAM RF-AGC */
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struct SCfgAgc m_qamIfAgcCfg; /**< settings for QAM IF-AGC */
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u16 m_qamPgaCfg; /**< settings for QAM PGA */
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struct SCfgPreSaw m_qamPreSawCfg; /**< settings for QAM pre SAW sense */
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enum EDrxkInterleaveMode m_qamInterleaveMode; /**< QAM Interleave mode */
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u16 m_fecRsPlen;
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u16 m_fecRsPrescale;
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enum DRXKCfgDvbtSqiSpeed m_sqiSpeed;
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u16 m_GPIO;
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u16 m_GPIOCfg;
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u16 m_GPIO;
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u16 m_GPIOCfg;
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struct SCfgAgc m_dvbtRfAgcCfg; ///< settings for QAM RF-AGC
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struct SCfgAgc m_dvbtIfAgcCfg; ///< settings for QAM IF-AGC
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struct SCfgPreSaw m_dvbtPreSawCfg; ///< settings for QAM pre SAW sense
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struct SCfgAgc m_dvbtRfAgcCfg; /**< settings for QAM RF-AGC */
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struct SCfgAgc m_dvbtIfAgcCfg; /**< settings for QAM IF-AGC */
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struct SCfgPreSaw m_dvbtPreSawCfg; /**< settings for QAM pre SAW sense */
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u16 m_agcFastClipCtrlDelay;
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bool m_adcCompPassed;
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u16 m_adcCompCoef[64];
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u16 m_adcState;
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u16 m_agcFastClipCtrlDelay;
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bool m_adcCompPassed;
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u16 m_adcCompCoef[64];
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u16 m_adcState;
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u8 *m_microcode;
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int m_microcode_length;
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bool m_DRXK_A1_PATCH_CODE;
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bool m_DRXK_A1_ROM_CODE;
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bool m_DRXK_A2_ROM_CODE;
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bool m_DRXK_A3_ROM_CODE;
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bool m_DRXK_A2_PATCH_CODE;
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bool m_DRXK_A3_PATCH_CODE;
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u8 *m_microcode;
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int m_microcode_length;
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bool m_DRXK_A1_PATCH_CODE;
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bool m_DRXK_A1_ROM_CODE;
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bool m_DRXK_A2_ROM_CODE;
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bool m_DRXK_A3_ROM_CODE;
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bool m_DRXK_A2_PATCH_CODE;
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bool m_DRXK_A3_PATCH_CODE;
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bool m_rfmirror;
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u8 m_deviceSpin;
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u32 m_iqmRcRate;
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bool m_rfmirror;
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u8 m_deviceSpin;
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u32 m_iqmRcRate;
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u16 m_AntennaDVBC;
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u16 m_AntennaDVBT;
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u16 m_AntennaSwitchDVBTDVBC;
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u16 m_AntennaDVBC;
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u16 m_AntennaDVBT;
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u16 m_AntennaSwitchDVBTDVBC;
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DRXPowerMode_t m_currentPowerMode;
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enum DRXPowerMode m_currentPowerMode;
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};
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#define NEVER_LOCK 0
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