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memory: tegra: Add Tegra30 memory controller hot resets

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Define the table of memory controller hot resets for Tegra30.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Dmitry Osipenko 2018-04-13 14:33:53 +03:00 committed by Thierry Reding
parent cb557757e1
commit ec4e1f0d66
1 changed files with 33 additions and 0 deletions
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33
drivers/memory/tegra/tegra30.c
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@ -960,6 +960,36 @@ static const struct tegra_smmu_soc tegra30_smmu_soc = {
.num_asids = 4,
};
#define TEGRA30_MC_RESET(_name, _control, _status, _bit) \
{ \
.name = #_name, \
.id = TEGRA30_MC_RESET_##_name, \
.control = _control, \
.status = _status, \
.bit = _bit, \
}
static const struct tegra_mc_reset tegra30_mc_resets[] = {
TEGRA30_MC_RESET(AFI, 0x200, 0x204, 0),
TEGRA30_MC_RESET(AVPC, 0x200, 0x204, 1),
TEGRA30_MC_RESET(DC, 0x200, 0x204, 2),
TEGRA30_MC_RESET(DCB, 0x200, 0x204, 3),
TEGRA30_MC_RESET(EPP, 0x200, 0x204, 4),
TEGRA30_MC_RESET(2D, 0x200, 0x204, 5),
TEGRA30_MC_RESET(HC, 0x200, 0x204, 6),
TEGRA30_MC_RESET(HDA, 0x200, 0x204, 7),
TEGRA30_MC_RESET(ISP, 0x200, 0x204, 8),
TEGRA30_MC_RESET(MPCORE, 0x200, 0x204, 9),
TEGRA30_MC_RESET(MPCORELP, 0x200, 0x204, 10),
TEGRA30_MC_RESET(MPE, 0x200, 0x204, 11),
TEGRA30_MC_RESET(3D, 0x200, 0x204, 12),
TEGRA30_MC_RESET(3D2, 0x200, 0x204, 13),
TEGRA30_MC_RESET(PPCS, 0x200, 0x204, 14),
TEGRA30_MC_RESET(SATA, 0x200, 0x204, 15),
TEGRA30_MC_RESET(VDE, 0x200, 0x204, 16),
TEGRA30_MC_RESET(VI, 0x200, 0x204, 17),
};
const struct tegra_mc_soc tegra30_mc_soc = {
.clients = tegra30_mc_clients,
.num_clients = ARRAY_SIZE(tegra30_mc_clients),
@ -969,4 +999,7 @@ const struct tegra_mc_soc tegra30_mc_soc = {
.smmu = &tegra30_smmu_soc,
.intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
MC_INT_DECERR_EMEM,
.reset_ops = &terga_mc_reset_ops_common,
.resets = tegra30_mc_resets,
.num_resets = ARRAY_SIZE(tegra30_mc_resets),
};