forked from luck/tmp_suning_uos_patched
KVM: arm/arm64: vgic-new: Add GICv3 MMIO handling framework
Create a new file called vgic-mmio-v3.c and describe the GICv3 distributor and redistributor registers there. This adds a special macro to deal with the split of SGI/PPI in the redistributor and SPIs in the distributor, which allows us to reuse the existing GICv2 handlers for those registers which are compatible. Also we provide a function to deal with the registration of the two separate redistributor frames per VCPU. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
This commit is contained in:
Andre Przywara
Christoffer Dall
parent
ed40213ef9
commit
ed9b8cefa9
224
virt/kvm/arm/vgic/vgic-mmio-v3.c
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224
virt/kvm/arm/vgic/vgic-mmio-v3.c
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@ -0,0 +1,224 @@
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/*
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* VGICv3 MMIO handling functions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/irqchip/arm-gic-v3.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <kvm/iodev.h>
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#include <kvm/arm_vgic.h>
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#include <asm/kvm_emulate.h>
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#include "vgic.h"
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#include "vgic-mmio.h"
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/*
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* The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
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* redistributors, while SPIs are covered by registers in the distributor
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* block. Trying to set private IRQs in this block gets ignored.
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* We take some special care here to fix the calculation of the register
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* offset.
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*/
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#define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, bpi, acc) \
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{ \
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.reg_offset = off, \
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.bits_per_irq = bpi, \
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.len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
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.access_flags = acc, \
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.read = vgic_mmio_read_raz, \
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.write = vgic_mmio_write_wi, \
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}, { \
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.reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
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.bits_per_irq = bpi, \
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.len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \
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.access_flags = acc, \
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.read = rd, \
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.write = wr, \
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}
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static const struct vgic_register_region vgic_v3_dist_registers[] = {
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REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 16,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
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vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
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vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
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vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
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vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
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vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
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vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
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vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
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vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
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vgic_mmio_read_config, vgic_mmio_write_config, 2,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 64,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 48,
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VGIC_ACCESS_32bit),
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};
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static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
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REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 48,
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VGIC_ACCESS_32bit),
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};
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static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
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REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0,
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vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0,
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vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
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vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_ISPENDR0,
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vgic_mmio_read_pending, vgic_mmio_write_spending, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_ICPENDR0,
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vgic_mmio_read_pending, vgic_mmio_write_cpending, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_ISACTIVER0,
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vgic_mmio_read_active, vgic_mmio_write_sactive, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_ICACTIVER0,
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vgic_mmio_read_active, vgic_mmio_write_cactive, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0,
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vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0,
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vgic_mmio_read_config, vgic_mmio_write_config, 8,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_NSACR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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};
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unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
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{
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dev->regions = vgic_v3_dist_registers;
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dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
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kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
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return SZ_64K;
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}
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int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t redist_base_address)
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{
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int nr_vcpus = atomic_read(&kvm->online_vcpus);
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struct kvm_vcpu *vcpu;
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struct vgic_io_device *devices;
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int c, ret = 0;
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devices = kmalloc(sizeof(struct vgic_io_device) * nr_vcpus * 2,
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GFP_KERNEL);
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if (!devices)
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return -ENOMEM;
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kvm_for_each_vcpu(c, vcpu, kvm) {
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gpa_t rd_base = redist_base_address + c * SZ_64K * 2;
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gpa_t sgi_base = rd_base + SZ_64K;
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struct vgic_io_device *rd_dev = &devices[c * 2];
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struct vgic_io_device *sgi_dev = &devices[c * 2 + 1];
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kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
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rd_dev->base_addr = rd_base;
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rd_dev->regions = vgic_v3_rdbase_registers;
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rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
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rd_dev->redist_vcpu = vcpu;
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mutex_lock(&kvm->slots_lock);
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ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
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SZ_64K, &rd_dev->dev);
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mutex_unlock(&kvm->slots_lock);
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if (ret)
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break;
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kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops);
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sgi_dev->base_addr = sgi_base;
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sgi_dev->regions = vgic_v3_sgibase_registers;
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sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers);
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sgi_dev->redist_vcpu = vcpu;
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mutex_lock(&kvm->slots_lock);
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ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base,
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SZ_64K, &sgi_dev->dev);
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mutex_unlock(&kvm->slots_lock);
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if (ret) {
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kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
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&rd_dev->dev);
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break;
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}
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}
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if (ret) {
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/* The current c failed, so we start with the previous one. */
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for (c--; c >= 0; c--) {
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kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
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&devices[c * 2].dev);
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kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
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&devices[c * 2 + 1].dev);
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}
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kfree(devices);
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} else {
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kvm->arch.vgic.redist_iodevs = devices;
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}
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return ret;
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}
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@ -478,6 +478,11 @@ int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
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case VGIC_V2:
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len = vgic_v2_init_dist_iodev(io_device);
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break;
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#ifdef CONFIG_KVM_ARM_VGIC_V3
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case VGIC_V3:
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len = vgic_v3_init_dist_iodev(io_device);
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break;
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#endif
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default:
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BUG_ON(1);
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}
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@ -145,4 +145,6 @@ void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
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unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev);
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unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev);
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#endif
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@ -42,6 +42,7 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
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void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
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void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
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void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
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int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t dist_base_address);
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#else
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static inline void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu)
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{
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@ -63,6 +64,12 @@ static inline void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
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static inline void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
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{
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}
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static inline int vgic_register_redist_iodevs(struct kvm *kvm,
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gpa_t dist_base_address)
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{
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return -ENODEV;
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}
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#endif
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#endif
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