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perf, x86: P4 PMU -- fix typo in unflagged NMI handling

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Tested-by: Lin Ming <ming.m.lin@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org>
Cc: Cyrill Gorcunov <gorcunov@gmail.com>
LKML-Reference: <1274174954.22793.17.camel@minggr.sh.intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
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Cyrill Gorcunov 2010-05-18 17:29:14 +08:00 committed by Ingo Molnar
parent 0db1a7bc00
commit ef4f30f54e
1 changed files with 1 additions and 1 deletions
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arch/x86/kernel/cpu/perf_event_p4.c
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@ -473,7 +473,7 @@ static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)
rdmsr(hwc->config_base + hwc->idx, low, high);
/* we need to check high bit for unflagged overflows */
if ((low & P4_CCCR_OVF) || (high & (1 << 31))) {
if ((low & P4_CCCR_OVF) || !(high & (1 << 31))) {
overflow = 1;
(void)checking_wrmsrl(hwc->config_base + hwc->idx,
((u64)low) & ~P4_CCCR_OVF);