forked from luck/tmp_suning_uos_patched
powerpc/perf: Add Power8 mem_access event to sysfs
Patch add "mem_access" event to sysfs. This as-is not a raw event supported by Power8 pmu. Instead, it is formed based on raw event encoding specificed in isa207-common.h. Primary PMU event used here is PM_MRK_INST_CMPL. This event tracks only the completed marked instructions. Random sampling mode (MMCRA[SM]) with Random Instruction Sampling (RIS) is enabled to mark type of instructions. With Random sampling in RLS mode with PM_MRK_INST_CMPL event, the LDST /DATA_SRC fields in SIER identifies the memory hierarchy level (eg: L1, L2 etc) statisfied a data-cache miss for a marked instruction. Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -89,3 +89,9 @@ EVENT(PM_MRK_FILT_MATCH, 0x2013c)
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EVENT(PM_MRK_FILT_MATCH_ALT, 0x3012e)
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/* Alternate event code for PM_LD_MISS_L1 */
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EVENT(PM_LD_MISS_L1_ALT, 0x400f0)
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/*
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* Memory Access Event -- mem_access
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* Primary PMU event used here is PM_MRK_INST_CMPL, along with
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* Random Load/Store Facility Sampling (RIS) in Random sampling mode (MMCRA[SM]).
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*/
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EVENT(MEM_ACCESS, 0x10401e0)
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@ -90,6 +90,7 @@ GENERIC_EVENT_ATTR(branch-instructions, PM_BRU_FIN);
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GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
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GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1);
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GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
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GENERIC_EVENT_ATTR(mem_access, MEM_ACCESS);
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CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
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CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
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@ -120,6 +121,7 @@ static struct attribute *power8_events_attr[] = {
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GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
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GENERIC_EVENT_PTR(PM_LD_REF_L1),
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GENERIC_EVENT_PTR(PM_LD_MISS_L1),
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GENERIC_EVENT_PTR(MEM_ACCESS),
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CACHE_EVENT_PTR(PM_LD_MISS_L1),
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CACHE_EVENT_PTR(PM_LD_REF_L1),
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