forked from luck/tmp_suning_uos_patched
PCI MSI: Refactor interrupt masking code
Since most of the callers already know whether they have an MSI or an MSI-X capability, split msi_set_mask_bits() into msi_mask_irq() and msix_mask_irq(). The only callers which don't (mask_msi_irq() and unmask_msi_irq()) can share code in msi_set_mask_bit(). This then becomes the only caller of msix_flush_writes(), so we can inline it. The flushing read can be to any address that belongs to the device, so we can eliminate the calculation too. We can also get rid of maskbits_mask from struct msi_desc and simply recalculate it on the rare occasion that we need it. The single-bit 'masked' element is replaced by a copy of the 32-bit 'masked' register, so this patch does not affect the size of msi_desc. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
This commit is contained in:
Matthew Wilcox
Jesse Barnes
parent
264d9caaa1
commit
f2440d9acb
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@ -105,17 +105,14 @@ static inline __attribute_const__ u32 msi_mask(unsigned x)
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return (1 << (1 << x)) - 1;
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}
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static void msix_flush_writes(struct irq_desc *desc)
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static inline __attribute_const__ u32 msi_capable_mask(u16 control)
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{
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struct msi_desc *entry;
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return msi_mask((control >> 1) & 7);
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}
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entry = get_irq_desc_msi(desc);
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BUG_ON(!entry);
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if (entry->msi_attrib.is_msix) {
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int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
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PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
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readl(entry->mask_base + offset);
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}
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static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
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{
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return msi_mask((control >> 4) & 7);
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}
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/*
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@ -127,32 +124,57 @@ static void msix_flush_writes(struct irq_desc *desc)
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* Returns 1 if it succeeded in masking the interrupt and 0 if the device
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* doesn't support MSI masking.
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*/
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static int msi_set_mask_bits(struct irq_desc *desc, u32 mask, u32 flag)
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static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
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{
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struct msi_desc *entry;
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u32 mask_bits = desc->masked;
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entry = get_irq_desc_msi(desc);
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BUG_ON(!entry);
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if (entry->msi_attrib.is_msix) {
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int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
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PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
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writel(flag, entry->mask_base + offset);
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readl(entry->mask_base + offset);
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if (!desc->msi_attrib.maskbit)
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return;
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mask_bits &= ~mask;
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mask_bits |= flag;
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pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
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desc->masked = mask_bits;
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}
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/*
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* This internal function does not flush PCI writes to the device.
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* All users must ensure that they read from the device before either
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* assuming that the device state is up to date, or returning out of this
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* file. This saves a few milliseconds when initialising devices with lots
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* of MSI-X interrupts.
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*/
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static void msix_mask_irq(struct msi_desc *desc, u32 flag)
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{
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u32 mask_bits = desc->masked;
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unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
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PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
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mask_bits &= ~1;
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mask_bits |= flag;
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writel(mask_bits, desc->mask_base + offset);
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desc->masked = mask_bits;
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}
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static void msi_set_mask_bit(unsigned irq, u32 flag)
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{
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struct msi_desc *desc = get_irq_msi(irq);
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if (desc->msi_attrib.is_msix) {
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msix_mask_irq(desc, flag);
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readl(desc->mask_base); /* Flush write to device */
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} else {
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int pos;
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u32 mask_bits;
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if (!entry->msi_attrib.maskbit)
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return 0;
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pos = entry->mask_pos;
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pci_read_config_dword(entry->dev, pos, &mask_bits);
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mask_bits &= ~mask;
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mask_bits |= flag & mask;
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pci_write_config_dword(entry->dev, pos, mask_bits);
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msi_mask_irq(desc, 1, flag);
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}
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entry->msi_attrib.masked = !!flag;
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return 1;
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}
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void mask_msi_irq(unsigned int irq)
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{
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msi_set_mask_bit(irq, 1);
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}
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void unmask_msi_irq(unsigned int irq)
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{
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msi_set_mask_bit(irq, 0);
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}
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void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
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@ -230,22 +252,6 @@ void write_msi_msg(unsigned int irq, struct msi_msg *msg)
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write_msi_msg_desc(desc, msg);
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}
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void mask_msi_irq(unsigned int irq)
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{
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struct irq_desc *desc = irq_to_desc(irq);
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msi_set_mask_bits(desc, 1, 1);
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msix_flush_writes(desc);
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}
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void unmask_msi_irq(unsigned int irq)
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{
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struct irq_desc *desc = irq_to_desc(irq);
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msi_set_mask_bits(desc, 1, 0);
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msix_flush_writes(desc);
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}
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static int msi_free_irqs(struct pci_dev* dev);
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static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
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@ -281,13 +287,9 @@ static void __pci_restore_msi_state(struct pci_dev *dev)
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pci_intx_for_msi(dev, 0);
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msi_set_enable(dev, 0);
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write_msi_msg(dev->irq, &entry->msg);
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if (entry->msi_attrib.maskbit) {
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struct irq_desc *desc = irq_to_desc(dev->irq);
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msi_set_mask_bits(desc, entry->msi_attrib.maskbits_mask,
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entry->msi_attrib.masked);
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}
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pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
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msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
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control &= ~PCI_MSI_FLAGS_QSIZE;
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control |= PCI_MSI_FLAGS_ENABLE;
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pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
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@ -307,9 +309,8 @@ static void __pci_restore_msix_state(struct pci_dev *dev)
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msix_set_enable(dev, 0);
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list_for_each_entry(entry, &dev->msi_list, list) {
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struct irq_desc *desc = irq_to_desc(entry->irq);
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write_msi_msg(entry->irq, &entry->msg);
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msi_set_mask_bits(desc, 1, entry->msi_attrib.masked);
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msix_mask_irq(entry, entry->masked);
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}
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BUG_ON(list_empty(&dev->msi_list));
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@ -342,6 +343,7 @@ static int msi_capability_init(struct pci_dev *dev)
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struct msi_desc *entry;
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int pos, ret;
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u16 control;
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unsigned mask;
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msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */
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@ -356,21 +358,16 @@ static int msi_capability_init(struct pci_dev *dev)
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entry->msi_attrib.is_64 = is_64bit_address(control);
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entry->msi_attrib.entry_nr = 0;
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entry->msi_attrib.maskbit = is_mask_bit_support(control);
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entry->msi_attrib.masked = 1;
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entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
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entry->msi_attrib.pos = pos;
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if (entry->msi_attrib.maskbit) {
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unsigned int base, maskbits, temp;
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base = msi_mask_bits_reg(pos, entry->msi_attrib.is_64);
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entry->mask_pos = base;
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/* All MSIs are unmasked by default, Mask them all */
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pci_read_config_dword(dev, base, &maskbits);
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temp = msi_mask((control & PCI_MSI_FLAGS_QMASK) >> 1);
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maskbits |= temp;
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pci_write_config_dword(dev, base, maskbits);
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entry->msi_attrib.maskbits_mask = temp;
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}
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entry->mask_pos = msi_mask_bits_reg(pos, entry->msi_attrib.is_64);
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/* All MSIs are unmasked by default, Mask them all */
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if (entry->msi_attrib.maskbit)
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pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
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mask = msi_capable_mask(control);
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msi_mask_irq(entry, mask, mask);
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list_add_tail(&entry->list, &dev->msi_list);
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/* Configure MSI capability structure */
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@ -435,11 +432,12 @@ static int msix_capability_init(struct pci_dev *dev,
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entry->msi_attrib.is_msix = 1;
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entry->msi_attrib.is_64 = 1;
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entry->msi_attrib.entry_nr = j;
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entry->msi_attrib.maskbit = 1;
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entry->msi_attrib.masked = 1;
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entry->msi_attrib.default_irq = dev->irq;
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entry->msi_attrib.pos = pos;
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entry->mask_base = base;
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entry->masked = readl(base + j * PCI_MSIX_ENTRY_SIZE +
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PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
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msix_mask_irq(entry, 1);
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list_add_tail(&entry->list, &dev->msi_list);
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}
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@ -556,9 +554,11 @@ int pci_enable_msi(struct pci_dev* dev)
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}
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EXPORT_SYMBOL(pci_enable_msi);
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void pci_msi_shutdown(struct pci_dev* dev)
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void pci_msi_shutdown(struct pci_dev *dev)
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{
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struct msi_desc *entry;
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struct msi_desc *desc;
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u32 mask;
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u16 ctrl;
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if (!pci_msi_enable || !dev || !dev->msi_enabled)
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return;
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@ -568,18 +568,13 @@ void pci_msi_shutdown(struct pci_dev* dev)
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dev->msi_enabled = 0;
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BUG_ON(list_empty(&dev->msi_list));
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entry = list_entry(dev->msi_list.next, struct msi_desc, list);
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/* Return the the pci reset with msi irqs unmasked */
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if (entry->msi_attrib.maskbit) {
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u32 mask = entry->msi_attrib.maskbits_mask;
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struct irq_desc *desc = irq_to_desc(dev->irq);
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msi_set_mask_bits(desc, mask, ~mask);
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}
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if (entry->msi_attrib.is_msix)
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return;
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desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
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pci_read_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &ctrl);
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mask = msi_capable_mask(ctrl);
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msi_mask_irq(desc, mask, ~mask);
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/* Restore dev->irq to its default pin-assertion irq */
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dev->irq = entry->msi_attrib.default_irq;
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dev->irq = desc->msi_attrib.default_irq;
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}
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void pci_disable_msi(struct pci_dev* dev)
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@ -22,14 +22,13 @@ struct msi_desc {
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struct {
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__u8 is_msix : 1;
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__u8 maskbit : 1; /* mask-pending bit supported ? */
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__u8 masked : 1;
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__u8 is_64 : 1; /* Address size: 0=32bit 1=64bit */
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__u8 pos; /* Location of the msi capability */
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__u16 entry_nr; /* specific enabled entry */
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__u32 maskbits_mask; /* mask bits mask */
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unsigned default_irq; /* default pre-assigned irq */
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}msi_attrib;
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} msi_attrib;
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u32 masked; /* mask bits */
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unsigned int irq;
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struct list_head list;
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