forked from luck/tmp_suning_uos_patched
sh_eth: use DMA barriers
Commit 7d7355f58b
("sh_eth: Ensure proper ordering of descriptor active
bit write/read") did the right thing but used too "heavy" barriers while
there were already "lighter" DMA barriers exactly for this case...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
73186df8d7
commit
f32bfb9a8c
@ -1416,7 +1416,7 @@ static int sh_eth_txfree(struct net_device *ndev)
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if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
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break;
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/* TACT bit must be checked before all the following reads */
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rmb();
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dma_rmb();
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netif_info(mdp, tx_done, ndev,
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"tx entry %d status 0x%08x\n",
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entry, edmac_to_cpu(mdp, txdesc->status));
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@ -1458,7 +1458,7 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
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rxdesc = &mdp->rx_ring[entry];
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while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
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/* RACT bit must be checked before all the following reads */
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rmb();
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dma_rmb();
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desc_status = edmac_to_cpu(mdp, rxdesc->status);
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pkt_len = rxdesc->frame_length;
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@ -1544,7 +1544,7 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
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skb_checksum_none_assert(skb);
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rxdesc->addr = dma_addr;
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}
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wmb(); /* RACT bit must be set after all the above writes */
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dma_wmb(); /* RACT bit must be set after all the above writes */
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if (entry >= mdp->num_rx_ring - 1)
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rxdesc->status |=
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cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDLE);
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@ -2403,7 +2403,7 @@ static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
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}
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txdesc->buffer_length = skb->len;
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wmb(); /* TACT bit must be set after all the above writes */
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dma_wmb(); /* TACT bit must be set after all the above writes */
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if (entry >= mdp->num_tx_ring - 1)
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txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
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else
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