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ARM: pm: some ARMv7 requires a dsb in resume to ensure correctness

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Add a dsb after the isb to ensure that the previous writes to the
CP15 registers take effect before we enable the MMU.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2011-08-27 00:37:38 +01:00
parent 1c0270cd3a
commit f35235a315
1 changed files with 1 additions and 0 deletions
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arch/arm/mm/proc-v7.S
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@ -255,6 +255,7 @@ ENTRY(cpu_v7_do_resume)
mcr p15, 0, r4, c10, c2, 0 @ write PRRR
mcr p15, 0, r5, c10, c2, 1 @ write NMRR
isb
dsb
mov r0, r9 @ control register
mov r2, r7, lsr #14 @ get TTB0 base
mov r2, r2, lsl #14