forked from luck/tmp_suning_uos_patched
Merge git://git.kernel.org/pub/scm/linux/kernel/git/czankel/xtensa-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/czankel/xtensa-2.6: xtensa: enable m41t80 driver in s6105_defconfig xtensa: add m41t62 rtc to s6105 platform xtensa: enable s6gmac in s6105_defconfig xtensa: s6105 specific configuration for s6gmac s6gmac: xtensa s6000 on-chip ethernet driver xtensa: support s6000 gpio irqs and alternate function selection xtensa: s6000 dma engine support xtensa: allow variant to initialize own irq chips xtensa: cache inquiry and unaligned cache handling functions
This commit is contained in:
Linus Torvalds
commit
f39cf0b783
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@ -263,7 +263,54 @@ CONFIG_HAVE_IDE=y
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# CONFIG_SCSI_NETLINK is not set
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# CONFIG_ATA is not set
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# CONFIG_MD is not set
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# CONFIG_NETDEVICES is not set
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CONFIG_NETDEVICES=y
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# CONFIG_DUMMY is not set
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# CONFIG_BONDING is not set
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# CONFIG_MACVLAN is not set
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# CONFIG_EQUALIZER is not set
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# CONFIG_TUN is not set
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# CONFIG_VETH is not set
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CONFIG_PHYLIB=y
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#
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# MII PHY device drivers
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#
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# CONFIG_MARVELL_PHY is not set
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# CONFIG_DAVICOM_PHY is not set
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# CONFIG_QSEMI_PHY is not set
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# CONFIG_LXT_PHY is not set
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# CONFIG_CICADA_PHY is not set
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# CONFIG_VITESSE_PHY is not set
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CONFIG_SMSC_PHY=y
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# CONFIG_BROADCOM_PHY is not set
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# CONFIG_ICPLUS_PHY is not set
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# CONFIG_REALTEK_PHY is not set
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# CONFIG_NATIONAL_PHY is not set
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# CONFIG_STE10XP is not set
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# CONFIG_LSI_ET1011C_PHY is not set
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# CONFIG_FIXED_PHY is not set
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# CONFIG_MDIO_BITBANG is not set
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# CONFIG_NET_ETHERNET is not set
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CONFIG_NETDEV_1000=y
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CONFIG_S6GMAC=y
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# CONFIG_NETDEV_10000 is not set
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#
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# Wireless LAN
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#
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# CONFIG_WLAN_PRE80211 is not set
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# CONFIG_WLAN_80211 is not set
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# CONFIG_IWLWIFI_LEDS is not set
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#
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# Enable WiMAX (Networking options) to see the WiMAX drivers
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#
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# CONFIG_WAN is not set
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# CONFIG_PPP is not set
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# CONFIG_SLIP is not set
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# CONFIG_NETCONSOLE is not set
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# CONFIG_NETPOLL is not set
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# CONFIG_NET_POLL_CONTROLLER is not set
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# CONFIG_ISDN is not set
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# CONFIG_PHONE is not set
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@ -304,8 +351,6 @@ CONFIG_UNIX98_PTYS=y
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# CONFIG_LEGACY_PTYS is not set
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# CONFIG_IPMI_HANDLER is not set
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# CONFIG_HW_RANDOM is not set
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# CONFIG_RTC is not set
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# CONFIG_GEN_RTC is not set
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# CONFIG_R3964 is not set
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# CONFIG_RAW_DRIVER is not set
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# CONFIG_TCG_TPM is not set
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@ -387,7 +432,59 @@ CONFIG_SSB_POSSIBLE=y
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# CONFIG_MEMSTICK is not set
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# CONFIG_NEW_LEDS is not set
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# CONFIG_ACCESSIBILITY is not set
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# CONFIG_RTC_CLASS is not set
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CONFIG_RTC_LIB=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_HCTOSYS=y
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CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
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# CONFIG_RTC_DEBUG is not set
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#
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# RTC interfaces
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#
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# CONFIG_RTC_INTF_SYSFS is not set
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# CONFIG_RTC_INTF_PROC is not set
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# CONFIG_RTC_INTF_DEV is not set
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# CONFIG_RTC_DRV_TEST is not set
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#
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# I2C RTC drivers
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#
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# CONFIG_RTC_DRV_DS1307 is not set
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# CONFIG_RTC_DRV_DS1374 is not set
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# CONFIG_RTC_DRV_DS1672 is not set
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# CONFIG_RTC_DRV_MAX6900 is not set
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# CONFIG_RTC_DRV_RS5C372 is not set
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# CONFIG_RTC_DRV_ISL1208 is not set
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# CONFIG_RTC_DRV_X1205 is not set
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# CONFIG_RTC_DRV_PCF8563 is not set
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# CONFIG_RTC_DRV_PCF8583 is not set
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CONFIG_RTC_DRV_M41T80=y
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# CONFIG_RTC_DRV_M41T80_WDT is not set
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# CONFIG_RTC_DRV_S35390A is not set
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# CONFIG_RTC_DRV_FM3130 is not set
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# CONFIG_RTC_DRV_RX8581 is not set
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#
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# SPI RTC drivers
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#
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#
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# Platform RTC drivers
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#
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# CONFIG_RTC_DRV_DS1286 is not set
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# CONFIG_RTC_DRV_DS1511 is not set
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# CONFIG_RTC_DRV_DS1553 is not set
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# CONFIG_RTC_DRV_DS1742 is not set
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# CONFIG_RTC_DRV_STK17TA8 is not set
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# CONFIG_RTC_DRV_M48T86 is not set
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# CONFIG_RTC_DRV_M48T35 is not set
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# CONFIG_RTC_DRV_M48T59 is not set
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# CONFIG_RTC_DRV_BQ4802 is not set
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# CONFIG_RTC_DRV_V3020 is not set
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#
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# on-CPU RTC drivers
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#
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# CONFIG_DMADEVICES is not set
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# CONFIG_UIO is not set
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# CONFIG_STAGING is not set
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|
|
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@ -155,5 +155,100 @@ extern void copy_from_user_page(struct vm_area_struct*, struct page*,
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#endif
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#define XTENSA_CACHEBLK_LOG2 29
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#define XTENSA_CACHEBLK_SIZE (1 << XTENSA_CACHEBLK_LOG2)
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#define XTENSA_CACHEBLK_MASK (7 << XTENSA_CACHEBLK_LOG2)
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#if XCHAL_HAVE_CACHEATTR
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static inline u32 xtensa_get_cacheattr(void)
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{
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u32 r;
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asm volatile(" rsr %0, CACHEATTR" : "=a"(r));
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return r;
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}
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static inline u32 xtensa_get_dtlb1(u32 addr)
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{
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u32 r = addr & XTENSA_CACHEBLK_MASK;
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return r | ((xtensa_get_cacheattr() >> (r >> (XTENSA_CACHEBLK_LOG2-2)))
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& 0xF);
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}
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#else
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static inline u32 xtensa_get_dtlb1(u32 addr)
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{
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u32 r;
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asm volatile(" rdtlb1 %0, %1" : "=a"(r) : "a"(addr));
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asm volatile(" dsync");
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return r;
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}
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static inline u32 xtensa_get_cacheattr(void)
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{
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u32 r = 0;
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u32 a = 0;
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do {
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a -= XTENSA_CACHEBLK_SIZE;
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r = (r << 4) | (xtensa_get_dtlb1(a) & 0xF);
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} while (a);
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return r;
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}
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#endif
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static inline int xtensa_need_flush_dma_source(u32 addr)
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{
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return (xtensa_get_dtlb1(addr) & ((1 << XCHAL_CA_BITS) - 1)) >= 4;
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}
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static inline int xtensa_need_invalidate_dma_destination(u32 addr)
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{
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return (xtensa_get_dtlb1(addr) & ((1 << XCHAL_CA_BITS) - 1)) != 2;
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}
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static inline void flush_dcache_unaligned(u32 addr, u32 size)
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{
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u32 cnt;
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if (size) {
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cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr)
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+ XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE;
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while (cnt--) {
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asm volatile(" dhwb %0, 0" : : "a"(addr));
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addr += XCHAL_DCACHE_LINESIZE;
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}
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asm volatile(" dsync");
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}
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}
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static inline void invalidate_dcache_unaligned(u32 addr, u32 size)
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{
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int cnt;
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if (size) {
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asm volatile(" dhwbi %0, 0 ;" : : "a"(addr));
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cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr)
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- XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE;
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while (cnt-- > 0) {
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asm volatile(" dhi %0, %1" : : "a"(addr),
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"n"(XCHAL_DCACHE_LINESIZE));
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addr += XCHAL_DCACHE_LINESIZE;
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}
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asm volatile(" dhwbi %0, %1" : : "a"(addr),
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"n"(XCHAL_DCACHE_LINESIZE));
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asm volatile(" dsync");
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}
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}
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static inline void flush_invalidate_dcache_unaligned(u32 addr, u32 size)
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{
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u32 cnt;
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if (size) {
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cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr)
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+ XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE;
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while (cnt--) {
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asm volatile(" dhwbi %0, 0" : : "a"(addr));
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addr += XCHAL_DCACHE_LINESIZE;
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}
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asm volatile(" dsync");
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}
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}
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#endif /* __KERNEL__ */
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#endif /* _XTENSA_CACHEFLUSH_H */
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@ -38,14 +38,14 @@ static inline int gpio_cansleep(unsigned int gpio)
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return __gpio_cansleep(gpio);
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}
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static inline int gpio_to_irq(unsigned int gpio)
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{
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return __gpio_to_irq(gpio);
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}
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/*
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* Not implemented, yet.
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*/
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static inline int gpio_to_irq(unsigned int gpio)
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{
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return -ENOSYS;
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}
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static inline int irq_to_gpio(unsigned int irq)
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{
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return -EINVAL;
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@ -11,6 +11,7 @@
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#ifndef _XTENSA_IRQ_H
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#define _XTENSA_IRQ_H
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#include <linux/init.h>
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#include <platform/hardware.h>
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#include <variant/core.h>
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@ -21,11 +22,20 @@ static inline void variant_irq_enable(unsigned int irq) { }
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static inline void variant_irq_disable(unsigned int irq) { }
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#endif
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#ifndef VARIANT_NR_IRQS
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# define VARIANT_NR_IRQS 0
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#endif
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#ifndef PLATFORM_NR_IRQS
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# define PLATFORM_NR_IRQS 0
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#endif
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#define XTENSA_NR_IRQS XCHAL_NUM_INTERRUPTS
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#define NR_IRQS (XTENSA_NR_IRQS + PLATFORM_NR_IRQS)
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#define NR_IRQS (XTENSA_NR_IRQS + VARIANT_NR_IRQS + PLATFORM_NR_IRQS)
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#if VARIANT_NR_IRQS == 0
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static inline void variant_init_irq(void) { }
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#else
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void variant_init_irq(void) __init;
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#endif
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static __inline__ int irq_canonicalize(int irq)
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{
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|
|
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|||
|
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@ -197,4 +197,6 @@ void __init init_IRQ(void)
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}
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cached_irq_mask = 0;
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variant_init_irq();
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}
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|
|
|
|||
|
|
@ -5,14 +5,27 @@
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*/
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#include <linux/kernel.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serial_8250.h>
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||||
|
||||
#include <variant/hardware.h>
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||||
#include <variant/dmac.h>
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|
||||
#include <platform/gpio.h>
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||||
|
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#define GPIO3_INTNUM 3
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#define UART_INTNUM 4
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#define GMAC_INTNUM 5
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|
||||
static const signed char gpio3_irq_mappings[] = {
|
||||
S6_INTC_GPIO(3),
|
||||
-1
|
||||
};
|
||||
|
||||
static const signed char uart_irq_mappings[] = {
|
||||
S6_INTC_UART(0),
|
||||
|
|
@ -20,8 +33,18 @@ static const signed char uart_irq_mappings[] = {
|
|||
-1,
|
||||
};
|
||||
|
||||
static const signed char gmac_irq_mappings[] = {
|
||||
S6_INTC_GMAC_STAT,
|
||||
S6_INTC_GMAC_ERR,
|
||||
S6_INTC_DMA_HOSTTERMCNT(0),
|
||||
S6_INTC_DMA_HOSTTERMCNT(1),
|
||||
-1
|
||||
};
|
||||
|
||||
const signed char *platform_irq_mappings[NR_IRQS] = {
|
||||
[GPIO3_INTNUM] = gpio3_irq_mappings,
|
||||
[UART_INTNUM] = uart_irq_mappings,
|
||||
[GMAC_INTNUM] = gmac_irq_mappings,
|
||||
};
|
||||
|
||||
static struct plat_serial8250_port serial_platform_data[] = {
|
||||
|
|
@ -46,6 +69,66 @@ static struct plat_serial8250_port serial_platform_data[] = {
|
|||
{ },
|
||||
};
|
||||
|
||||
static struct resource s6_gmac_resource[] = {
|
||||
{
|
||||
.name = "mem",
|
||||
.start = (resource_size_t)S6_REG_GMAC,
|
||||
.end = (resource_size_t)S6_REG_GMAC + 0x10000 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.name = "dma",
|
||||
.start = (resource_size_t)
|
||||
DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACTX),
|
||||
.end = (resource_size_t)
|
||||
DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACTX) + 0x100 - 1,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
{
|
||||
.name = "dma",
|
||||
.start = (resource_size_t)
|
||||
DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACRX),
|
||||
.end = (resource_size_t)
|
||||
DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACRX) + 0x100 - 1,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
{
|
||||
.name = "io",
|
||||
.start = (resource_size_t)S6_MEM_GMAC,
|
||||
.end = (resource_size_t)S6_MEM_GMAC + 0x2000000 - 1,
|
||||
.flags = IORESOURCE_IO,
|
||||
},
|
||||
{
|
||||
.name = "irq",
|
||||
.start = (resource_size_t)GMAC_INTNUM,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.name = "irq",
|
||||
.start = (resource_size_t)PHY_POLL,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init prepare_phy_irq(int pin)
|
||||
{
|
||||
int irq;
|
||||
if (gpio_request(pin, "s6gmac_phy") < 0)
|
||||
goto fail;
|
||||
if (gpio_direction_input(pin) < 0)
|
||||
goto free;
|
||||
irq = gpio_to_irq(pin);
|
||||
if (irq < 0)
|
||||
goto free;
|
||||
if (set_irq_type(irq, IRQ_TYPE_LEVEL_LOW) < 0)
|
||||
goto free;
|
||||
return irq;
|
||||
free:
|
||||
gpio_free(pin);
|
||||
fail:
|
||||
return PHY_POLL;
|
||||
}
|
||||
|
||||
static struct platform_device platform_devices[] = {
|
||||
{
|
||||
.name = "serial8250",
|
||||
|
|
@ -54,12 +137,23 @@ static struct platform_device platform_devices[] = {
|
|||
.platform_data = serial_platform_data,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "s6gmac",
|
||||
.id = 0,
|
||||
.resource = s6_gmac_resource,
|
||||
.num_resources = ARRAY_SIZE(s6_gmac_resource),
|
||||
},
|
||||
{
|
||||
I2C_BOARD_INFO("m41t62", S6I2C_ADDR_M41T62),
|
||||
},
|
||||
};
|
||||
|
||||
static int __init device_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
s6_gmac_resource[5].start = prepare_phy_irq(GPIO_PHY_IRQ);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(platform_devices); i++)
|
||||
platform_device_register(&platform_devices[i]);
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -35,12 +35,21 @@ void __init platform_setup(char **cmdline)
|
|||
{
|
||||
unsigned long reg;
|
||||
|
||||
reg = readl(S6_REG_GREG1 + S6_GREG1_PLLSEL);
|
||||
reg &= ~(S6_GREG1_PLLSEL_GMAC_MASK << S6_GREG1_PLLSEL_GMAC |
|
||||
S6_GREG1_PLLSEL_GMII_MASK << S6_GREG1_PLLSEL_GMII);
|
||||
reg |= S6_GREG1_PLLSEL_GMAC_125MHZ << S6_GREG1_PLLSEL_GMAC |
|
||||
S6_GREG1_PLLSEL_GMII_125MHZ << S6_GREG1_PLLSEL_GMII;
|
||||
writel(reg, S6_REG_GREG1 + S6_GREG1_PLLSEL);
|
||||
|
||||
reg = readl(S6_REG_GREG1 + S6_GREG1_CLKGATE);
|
||||
reg &= ~(1 << S6_GREG1_BLOCK_SB);
|
||||
reg &= ~(1 << S6_GREG1_BLOCK_GMAC);
|
||||
writel(reg, S6_REG_GREG1 + S6_GREG1_CLKGATE);
|
||||
|
||||
reg = readl(S6_REG_GREG1 + S6_GREG1_BLOCKENA);
|
||||
reg |= 1 << S6_GREG1_BLOCK_SB;
|
||||
reg |= 1 << S6_GREG1_BLOCK_GMAC;
|
||||
writel(reg, S6_REG_GREG1 + S6_GREG1_BLOCKENA);
|
||||
|
||||
printk(KERN_NOTICE "S6105 on Stretch S6000 - "
|
||||
|
|
@ -49,7 +58,7 @@ void __init platform_setup(char **cmdline)
|
|||
|
||||
void __init platform_init(bp_tag_t *first)
|
||||
{
|
||||
s6_gpio_init();
|
||||
s6_gpio_init(0);
|
||||
gpio_request(GPIO_LED1_NGREEN, "led1_green");
|
||||
gpio_request(GPIO_LED1_RED, "led1_red");
|
||||
gpio_direction_output(GPIO_LED1_NGREEN, 1);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# s6000 Makefile
|
||||
|
||||
obj-y += irq.o gpio.o
|
||||
obj-y += irq.o gpio.o dmac.o
|
||||
obj-$(CONFIG_XTENSA_CALIBRATE_CCOUNT) += delay.o
|
||||
|
|
|
|||
173
arch/xtensa/variants/s6000/dmac.c
Normal file
173
arch/xtensa/variants/s6000/dmac.c
Normal file
|
|
@ -0,0 +1,173 @@
|
|||
/*
|
||||
* Authors: Oskar Schirmer <os@emlix.com>
|
||||
* Daniel Gloeckner <dg@emlix.com>
|
||||
* (c) 2008 emlix GmbH http://www.emlix.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <variant/dmac.h>
|
||||
|
||||
/* DMA engine lookup */
|
||||
|
||||
struct s6dmac_ctrl s6dmac_ctrl[S6_DMAC_NB];
|
||||
|
||||
|
||||
/* DMA control, per engine */
|
||||
|
||||
void s6dmac_put_fifo_cache(u32 dmac, int chan, u32 src, u32 dst, u32 size)
|
||||
{
|
||||
if (xtensa_need_flush_dma_source(src)) {
|
||||
u32 base = src;
|
||||
u32 span = size;
|
||||
u32 chunk = readl(DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK);
|
||||
if (chunk && (size > chunk)) {
|
||||
s32 skip =
|
||||
readl(DMA_CHNL(dmac, chan) + S6_DMA_SRCSKIP);
|
||||
u32 gaps = (size+chunk-1)/chunk - 1;
|
||||
if (skip >= 0) {
|
||||
span += gaps * skip;
|
||||
} else if (-skip > chunk) {
|
||||
s32 decr = gaps * (chunk + skip);
|
||||
base += decr;
|
||||
span = chunk - decr;
|
||||
} else {
|
||||
span = max(span + gaps * skip,
|
||||
(chunk + skip) * gaps - skip);
|
||||
}
|
||||
}
|
||||
flush_dcache_unaligned(base, span);
|
||||
}
|
||||
if (xtensa_need_invalidate_dma_destination(dst)) {
|
||||
u32 base = dst;
|
||||
u32 span = size;
|
||||
u32 chunk = readl(DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK);
|
||||
if (chunk && (size > chunk)) {
|
||||
s32 skip =
|
||||
readl(DMA_CHNL(dmac, chan) + S6_DMA_DSTSKIP);
|
||||
u32 gaps = (size+chunk-1)/chunk - 1;
|
||||
if (skip >= 0) {
|
||||
span += gaps * skip;
|
||||
} else if (-skip > chunk) {
|
||||
s32 decr = gaps * (chunk + skip);
|
||||
base += decr;
|
||||
span = chunk - decr;
|
||||
} else {
|
||||
span = max(span + gaps * skip,
|
||||
(chunk + skip) * gaps - skip);
|
||||
}
|
||||
}
|
||||
invalidate_dcache_unaligned(base, span);
|
||||
}
|
||||
s6dmac_put_fifo(dmac, chan, src, dst, size);
|
||||
}
|
||||
|
||||
void s6dmac_disable_error_irqs(u32 dmac, u32 mask)
|
||||
{
|
||||
unsigned long flags;
|
||||
spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock;
|
||||
spin_lock_irqsave(spinl, flags);
|
||||
_s6dmac_disable_error_irqs(dmac, mask);
|
||||
spin_unlock_irqrestore(spinl, flags);
|
||||
}
|
||||
|
||||
u32 s6dmac_int_sources(u32 dmac, u32 channel)
|
||||
{
|
||||
u32 mask, ret, tmp;
|
||||
mask = 1 << channel;
|
||||
|
||||
tmp = readl(dmac + S6_DMA_TERMCNTIRQSTAT);
|
||||
tmp &= mask;
|
||||
writel(tmp, dmac + S6_DMA_TERMCNTIRQCLR);
|
||||
ret = tmp >> channel;
|
||||
|
||||
tmp = readl(dmac + S6_DMA_PENDCNTIRQSTAT);
|
||||
tmp &= mask;
|
||||
writel(tmp, dmac + S6_DMA_PENDCNTIRQCLR);
|
||||
ret |= (tmp >> channel) << 1;
|
||||
|
||||
tmp = readl(dmac + S6_DMA_LOWWMRKIRQSTAT);
|
||||
tmp &= mask;
|
||||
writel(tmp, dmac + S6_DMA_LOWWMRKIRQCLR);
|
||||
ret |= (tmp >> channel) << 2;
|
||||
|
||||
tmp = readl(dmac + S6_DMA_INTRAW0);
|
||||
tmp &= (mask << S6_DMA_INT0_OVER) | (mask << S6_DMA_INT0_UNDER);
|
||||
writel(tmp, dmac + S6_DMA_INTCLEAR0);
|
||||
|
||||
if (tmp & (mask << S6_DMA_INT0_UNDER))
|
||||
ret |= 1 << 3;
|
||||
if (tmp & (mask << S6_DMA_INT0_OVER))
|
||||
ret |= 1 << 4;
|
||||
|
||||
tmp = readl(dmac + S6_DMA_MASTERERRINFO);
|
||||
mask <<= S6_DMA_INT1_CHANNEL;
|
||||
if (((tmp >> S6_DMA_MASTERERR_CHAN(0)) & S6_DMA_MASTERERR_CHAN_MASK)
|
||||
== channel)
|
||||
mask |= 1 << S6_DMA_INT1_MASTER;
|
||||
if (((tmp >> S6_DMA_MASTERERR_CHAN(1)) & S6_DMA_MASTERERR_CHAN_MASK)
|
||||
== channel)
|
||||
mask |= 1 << (S6_DMA_INT1_MASTER + 1);
|
||||
if (((tmp >> S6_DMA_MASTERERR_CHAN(2)) & S6_DMA_MASTERERR_CHAN_MASK)
|
||||
== channel)
|
||||
mask |= 1 << (S6_DMA_INT1_MASTER + 2);
|
||||
|
||||
tmp = readl(dmac + S6_DMA_INTRAW1) & mask;
|
||||
writel(tmp, dmac + S6_DMA_INTCLEAR1);
|
||||
ret |= ((tmp >> channel) & 1) << 5;
|
||||
ret |= ((tmp >> S6_DMA_INT1_MASTER) & S6_DMA_INT1_MASTER_MASK) << 6;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void s6dmac_release_chan(u32 dmac, int chan)
|
||||
{
|
||||
if (chan >= 0)
|
||||
s6dmac_disable_chan(dmac, chan);
|
||||
}
|
||||
|
||||
|
||||
/* global init */
|
||||
|
||||
static inline void __init dmac_init(u32 dmac, u8 chan_nb)
|
||||
{
|
||||
s6dmac_ctrl[S6_DMAC_INDEX(dmac)].dmac = dmac;
|
||||
spin_lock_init(&s6dmac_ctrl[S6_DMAC_INDEX(dmac)].lock);
|
||||
s6dmac_ctrl[S6_DMAC_INDEX(dmac)].chan_nb = chan_nb;
|
||||
writel(S6_DMA_INT1_MASTER_MASK << S6_DMA_INT1_MASTER,
|
||||
dmac + S6_DMA_INTCLEAR1);
|
||||
}
|
||||
|
||||
static inline void __init dmac_master(u32 dmac,
|
||||
u32 m0start, u32 m0end, u32 m1start, u32 m1end)
|
||||
{
|
||||
writel(m0start, dmac + S6_DMA_MASTER0START);
|
||||
writel(m0end - 1, dmac + S6_DMA_MASTER0END);
|
||||
writel(m1start, dmac + S6_DMA_MASTER1START);
|
||||
writel(m1end - 1, dmac + S6_DMA_MASTER1END);
|
||||
}
|
||||
|
||||
static void __init s6_dmac_init(void)
|
||||
{
|
||||
dmac_init(S6_REG_LMSDMA, S6_LMSDMA_NB);
|
||||
dmac_master(S6_REG_LMSDMA,
|
||||
S6_MEM_DDR, S6_MEM_PCIE_APER, S6_MEM_EFI, S6_MEM_GMAC);
|
||||
dmac_init(S6_REG_NIDMA, S6_NIDMA_NB);
|
||||
dmac_init(S6_REG_DPDMA, S6_DPDMA_NB);
|
||||
dmac_master(S6_REG_DPDMA,
|
||||
S6_MEM_DDR, S6_MEM_PCIE_APER, S6_REG_DP, S6_REG_DPDMA);
|
||||
dmac_init(S6_REG_HIFDMA, S6_HIFDMA_NB);
|
||||
dmac_master(S6_REG_HIFDMA,
|
||||
S6_MEM_GMAC, S6_MEM_PCIE_CFG, S6_MEM_PCIE_APER, S6_MEM_AUX);
|
||||
}
|
||||
|
||||
arch_initcall(s6_dmac_init);
|
||||
|
|
@ -4,15 +4,20 @@
|
|||
* Copyright (c) 2009 emlix GmbH
|
||||
* Authors: Oskar Schirmer <os@emlix.com>
|
||||
* Johannes Weiner <jw@emlix.com>
|
||||
* Daniel Gloeckner <dg@emlix.com>
|
||||
*/
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <variant/hardware.h>
|
||||
|
||||
#define IRQ_BASE XTENSA_NR_IRQS
|
||||
|
||||
#define S6_GPIO_DATA 0x000
|
||||
#define S6_GPIO_IS 0x404
|
||||
#define S6_GPIO_IBE 0x408
|
||||
|
|
@ -52,19 +57,175 @@ static void set(struct gpio_chip *chip, unsigned int off, int val)
|
|||
writeb(val ? ~0 : 0, S6_REG_GPIO + S6_GPIO_DATA + S6_GPIO_OFFSET(off));
|
||||
}
|
||||
|
||||
static int to_irq(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
if (offset < 8)
|
||||
return offset + IRQ_BASE;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static struct gpio_chip gpiochip = {
|
||||
.owner = THIS_MODULE,
|
||||
.direction_input = direction_input,
|
||||
.get = get,
|
||||
.direction_output = direction_output,
|
||||
.set = set,
|
||||
.to_irq = to_irq,
|
||||
.base = 0,
|
||||
.ngpio = 24,
|
||||
.can_sleep = 0, /* no blocking io needed */
|
||||
.exported = 0, /* no exporting to userspace */
|
||||
};
|
||||
|
||||
int s6_gpio_init(void)
|
||||
int s6_gpio_init(u32 afsel)
|
||||
{
|
||||
writeb(afsel, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_AFSEL);
|
||||
writeb(afsel >> 8, S6_REG_GPIO + S6_GPIO_BANK(1) + S6_GPIO_AFSEL);
|
||||
writeb(afsel >> 16, S6_REG_GPIO + S6_GPIO_BANK(2) + S6_GPIO_AFSEL);
|
||||
return gpiochip_add(&gpiochip);
|
||||
}
|
||||
|
||||
static void ack(unsigned int irq)
|
||||
{
|
||||
writeb(1 << (irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC);
|
||||
}
|
||||
|
||||
static void mask(unsigned int irq)
|
||||
{
|
||||
u8 r = readb(S6_REG_GPIO + S6_GPIO_IE);
|
||||
r &= ~(1 << (irq - IRQ_BASE));
|
||||
writeb(r, S6_REG_GPIO + S6_GPIO_IE);
|
||||
}
|
||||
|
||||
static void unmask(unsigned int irq)
|
||||
{
|
||||
u8 m = readb(S6_REG_GPIO + S6_GPIO_IE);
|
||||
m |= 1 << (irq - IRQ_BASE);
|
||||
writeb(m, S6_REG_GPIO + S6_GPIO_IE);
|
||||
}
|
||||
|
||||
static int set_type(unsigned int irq, unsigned int type)
|
||||
{
|
||||
const u8 m = 1 << (irq - IRQ_BASE);
|
||||
irq_flow_handler_t handler;
|
||||
struct irq_desc *desc;
|
||||
u8 reg;
|
||||
|
||||
if (type == IRQ_TYPE_PROBE) {
|
||||
if ((readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_AFSEL) & m)
|
||||
|| (readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IE) & m)
|
||||
|| readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_DIR
|
||||
+ S6_GPIO_MASK(irq - IRQ_BASE)))
|
||||
return 0;
|
||||
type = IRQ_TYPE_EDGE_BOTH;
|
||||
}
|
||||
|
||||
reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS);
|
||||
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) {
|
||||
reg |= m;
|
||||
handler = handle_level_irq;
|
||||
} else {
|
||||
reg &= ~m;
|
||||
handler = handle_edge_irq;
|
||||
}
|
||||
writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS);
|
||||
desc = irq_to_desc(irq);
|
||||
desc->handle_irq = handler;
|
||||
|
||||
reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV);
|
||||
if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING))
|
||||
reg |= m;
|
||||
else
|
||||
reg &= ~m;
|
||||
writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV);
|
||||
|
||||
reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IBE);
|
||||
if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
|
||||
reg |= m;
|
||||
else
|
||||
reg &= ~m;
|
||||
writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IBE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_chip gpioirqs = {
|
||||
.name = "GPIO",
|
||||
.ack = ack,
|
||||
.mask = mask,
|
||||
.unmask = unmask,
|
||||
.set_type = set_type,
|
||||
};
|
||||
|
||||
static u8 demux_masks[4];
|
||||
|
||||
static void demux_irqs(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
u8 *mask = get_irq_desc_data(desc);
|
||||
u8 pending;
|
||||
int cirq;
|
||||
|
||||
desc->chip->mask(irq);
|
||||
desc->chip->ack(irq);
|
||||
pending = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_MIS) & *mask;
|
||||
cirq = IRQ_BASE - 1;
|
||||
while (pending) {
|
||||
int n = ffs(pending);
|
||||
cirq += n;
|
||||
pending >>= n;
|
||||
generic_handle_irq(cirq);
|
||||
}
|
||||
desc->chip->unmask(irq);
|
||||
}
|
||||
|
||||
extern const signed char *platform_irq_mappings[XTENSA_NR_IRQS];
|
||||
|
||||
void __init variant_init_irq(void)
|
||||
{
|
||||
int irq, n;
|
||||
writeb(0, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IE);
|
||||
for (irq = n = 0; irq < XTENSA_NR_IRQS; irq++) {
|
||||
const signed char *mapping = platform_irq_mappings[irq];
|
||||
int alone = 1;
|
||||
u8 mask;
|
||||
if (!mapping)
|
||||
continue;
|
||||
for(mask = 0; *mapping != -1; mapping++)
|
||||
switch (*mapping) {
|
||||
case S6_INTC_GPIO(0):
|
||||
mask |= 1 << 0;
|
||||
break;
|
||||
case S6_INTC_GPIO(1):
|
||||
mask |= 1 << 1;
|
||||
break;
|
||||
case S6_INTC_GPIO(2):
|
||||
mask |= 1 << 2;
|
||||
break;
|
||||
case S6_INTC_GPIO(3):
|
||||
mask |= 0x1f << 3;
|
||||
break;
|
||||
default:
|
||||
alone = 0;
|
||||
}
|
||||
if (mask) {
|
||||
int cirq, i;
|
||||
if (!alone) {
|
||||
printk(KERN_ERR "chained irq chips can't share"
|
||||
" parent irq %i\n", irq);
|
||||
continue;
|
||||
}
|
||||
demux_masks[n] = mask;
|
||||
cirq = IRQ_BASE - 1;
|
||||
do {
|
||||
i = ffs(mask);
|
||||
cirq += i;
|
||||
mask >>= i;
|
||||
set_irq_chip(cirq, &gpioirqs);
|
||||
set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
|
||||
} while (mask);
|
||||
set_irq_data(irq, demux_masks + n);
|
||||
set_irq_chained_handler(irq, demux_irqs);
|
||||
if (++n == ARRAY_SIZE(demux_masks))
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
387
arch/xtensa/variants/s6000/include/variant/dmac.h
Normal file
387
arch/xtensa/variants/s6000/include/variant/dmac.h
Normal file
|
|
@ -0,0 +1,387 @@
|
|||
/*
|
||||
* include/asm-xtensa/variant-s6000/dmac.h
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2006 Tensilica Inc.
|
||||
* Copyright (C) 2008 Emlix GmbH <info@emlix.com>
|
||||
* Authors: Fabian Godehardt <fg@emlix.com>
|
||||
* Oskar Schirmer <os@emlix.com>
|
||||
* Daniel Gloeckner <dg@emlix.com>
|
||||
*/
|
||||
|
||||
#ifndef __ASM_XTENSA_S6000_DMAC_H
|
||||
#define __ASM_XTENSA_S6000_DMAC_H
|
||||
#include <linux/io.h>
|
||||
#include <variant/hardware.h>
|
||||
|
||||
/* DMA global */
|
||||
|
||||
#define S6_DMA_INTSTAT0 0x000
|
||||
#define S6_DMA_INTSTAT1 0x004
|
||||
#define S6_DMA_INTENABLE0 0x008
|
||||
#define S6_DMA_INTENABLE1 0x00C
|
||||
#define S6_DMA_INTRAW0 0x010
|
||||
#define S6_DMA_INTRAW1 0x014
|
||||
#define S6_DMA_INTCLEAR0 0x018
|
||||
#define S6_DMA_INTCLEAR1 0x01C
|
||||
#define S6_DMA_INTSET0 0x020
|
||||
#define S6_DMA_INTSET1 0x024
|
||||
#define S6_DMA_INT0_UNDER 0
|
||||
#define S6_DMA_INT0_OVER 16
|
||||
#define S6_DMA_INT1_CHANNEL 0
|
||||
#define S6_DMA_INT1_MASTER 16
|
||||
#define S6_DMA_INT1_MASTER_MASK 7
|
||||
#define S6_DMA_TERMCNTIRQSTAT 0x028
|
||||
#define S6_DMA_TERMCNTIRQCLR 0x02C
|
||||
#define S6_DMA_TERMCNTIRQSET 0x030
|
||||
#define S6_DMA_PENDCNTIRQSTAT 0x034
|
||||
#define S6_DMA_PENDCNTIRQCLR 0x038
|
||||
#define S6_DMA_PENDCNTIRQSET 0x03C
|
||||
#define S6_DMA_LOWWMRKIRQSTAT 0x040
|
||||
#define S6_DMA_LOWWMRKIRQCLR 0x044
|
||||
#define S6_DMA_LOWWMRKIRQSET 0x048
|
||||
#define S6_DMA_MASTERERRINFO 0x04C
|
||||
#define S6_DMA_MASTERERR_CHAN(n) (4*(n))
|
||||
#define S6_DMA_MASTERERR_CHAN_MASK 0xF
|
||||
#define S6_DMA_DESCRFIFO0 0x050
|
||||
#define S6_DMA_DESCRFIFO1 0x054
|
||||
#define S6_DMA_DESCRFIFO2 0x058
|
||||
#define S6_DMA_DESCRFIFO2_AUTODISABLE 24
|
||||
#define S6_DMA_DESCRFIFO3 0x05C
|
||||
#define S6_DMA_MASTER0START 0x060
|
||||
#define S6_DMA_MASTER0END 0x064
|
||||
#define S6_DMA_MASTER1START 0x068
|
||||
#define S6_DMA_MASTER1END 0x06C
|
||||
#define S6_DMA_NEXTFREE 0x070
|
||||
#define S6_DMA_NEXTFREE_CHAN 0
|
||||
#define S6_DMA_NEXTFREE_CHAN_MASK 0x1F
|
||||
#define S6_DMA_NEXTFREE_ENA 16
|
||||
#define S6_DMA_NEXTFREE_ENA_MASK ((1 << 16) - 1)
|
||||
#define S6_DMA_DPORTCTRLGRP(p) ((p) * 4 + 0x074)
|
||||
#define S6_DMA_DPORTCTRLGRP_FRAMEREP 0
|
||||
#define S6_DMA_DPORTCTRLGRP_NRCHANS 1
|
||||
#define S6_DMA_DPORTCTRLGRP_NRCHANS_1 0
|
||||
#define S6_DMA_DPORTCTRLGRP_NRCHANS_3 1
|
||||
#define S6_DMA_DPORTCTRLGRP_NRCHANS_4 2
|
||||
#define S6_DMA_DPORTCTRLGRP_NRCHANS_2 3
|
||||
#define S6_DMA_DPORTCTRLGRP_ENA 31
|
||||
|
||||
|
||||
/* DMA per channel */
|
||||
|
||||
#define DMA_CHNL(dmac, n) ((dmac) + 0x1000 + (n) * 0x100)
|
||||
#define DMA_INDEX_CHNL(addr) (((addr) >> 8) & 0xF)
|
||||
#define DMA_MASK_DMAC(addr) ((addr) & 0xFFFF0000)
|
||||
#define S6_DMA_CHNCTRL 0x000
|
||||
#define S6_DMA_CHNCTRL_ENABLE 0
|
||||
#define S6_DMA_CHNCTRL_PAUSE 1
|
||||
#define S6_DMA_CHNCTRL_PRIO 2
|
||||
#define S6_DMA_CHNCTRL_PRIO_MASK 3
|
||||
#define S6_DMA_CHNCTRL_PERIPHXFER 4
|
||||
#define S6_DMA_CHNCTRL_PERIPHENA 5
|
||||
#define S6_DMA_CHNCTRL_SRCINC 6
|
||||
#define S6_DMA_CHNCTRL_DSTINC 7
|
||||
#define S6_DMA_CHNCTRL_BURSTLOG 8
|
||||
#define S6_DMA_CHNCTRL_BURSTLOG_MASK 7
|
||||
#define S6_DMA_CHNCTRL_DESCFIFODEPTH 12
|
||||
#define S6_DMA_CHNCTRL_DESCFIFODEPTH_MASK 0x1F
|
||||
#define S6_DMA_CHNCTRL_DESCFIFOFULL 17
|
||||
#define S6_DMA_CHNCTRL_BWCONSEL 18
|
||||
#define S6_DMA_CHNCTRL_BWCONENA 19
|
||||
#define S6_DMA_CHNCTRL_PENDGCNTSTAT 20
|
||||
#define S6_DMA_CHNCTRL_PENDGCNTSTAT_MASK 0x3F
|
||||
#define S6_DMA_CHNCTRL_LOWWMARK 26
|
||||
#define S6_DMA_CHNCTRL_LOWWMARK_MASK 0xF
|
||||
#define S6_DMA_CHNCTRL_TSTAMP 30
|
||||
#define S6_DMA_TERMCNTNB 0x004
|
||||
#define S6_DMA_TERMCNTNB_MASK 0xFFFF
|
||||
#define S6_DMA_TERMCNTTMO 0x008
|
||||
#define S6_DMA_TERMCNTSTAT 0x00C
|
||||
#define S6_DMA_TERMCNTSTAT_MASK 0xFF
|
||||
#define S6_DMA_CMONCHUNK 0x010
|
||||
#define S6_DMA_SRCSKIP 0x014
|
||||
#define S6_DMA_DSTSKIP 0x018
|
||||
#define S6_DMA_CUR_SRC 0x024
|
||||
#define S6_DMA_CUR_DST 0x028
|
||||
#define S6_DMA_TIMESTAMP 0x030
|
||||
|
||||
/* DMA channel lists */
|
||||
|
||||
#define S6_DPDMA_CHAN(stream, channel) (4 * (stream) + (channel))
|
||||
#define S6_DPDMA_NB 16
|
||||
|
||||
#define S6_HIFDMA_GMACTX 0
|
||||
#define S6_HIFDMA_GMACRX 1
|
||||
#define S6_HIFDMA_I2S0 2
|
||||
#define S6_HIFDMA_I2S1 3
|
||||
#define S6_HIFDMA_EGIB 4
|
||||
#define S6_HIFDMA_PCITX 5
|
||||
#define S6_HIFDMA_PCIRX 6
|
||||
#define S6_HIFDMA_NB 7
|
||||
|
||||
#define S6_NIDMA_NB 4
|
||||
|
||||
#define S6_LMSDMA_NB 12
|
||||
|
||||
/* controller access */
|
||||
|
||||
#define S6_DMAC_NB 4
|
||||
#define S6_DMAC_INDEX(dmac) (((unsigned)(dmac) >> 18) % S6_DMAC_NB)
|
||||
|
||||
struct s6dmac_ctrl {
|
||||
u32 dmac;
|
||||
spinlock_t lock;
|
||||
u8 chan_nb;
|
||||
};
|
||||
|
||||
extern struct s6dmac_ctrl s6dmac_ctrl[S6_DMAC_NB];
|
||||
|
||||
|
||||
/* DMA control, per channel */
|
||||
|
||||
static inline int s6dmac_fifo_full(u32 dmac, int chan)
|
||||
{
|
||||
return (readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL)
|
||||
& (1 << S6_DMA_CHNCTRL_DESCFIFOFULL)) && 1;
|
||||
}
|
||||
|
||||
static inline int s6dmac_termcnt_irq(u32 dmac, int chan)
|
||||
{
|
||||
u32 m = 1 << chan;
|
||||
int r = (readl(dmac + S6_DMA_TERMCNTIRQSTAT) & m) && 1;
|
||||
if (r)
|
||||
writel(m, dmac + S6_DMA_TERMCNTIRQCLR);
|
||||
return r;
|
||||
}
|
||||
|
||||
static inline int s6dmac_pendcnt_irq(u32 dmac, int chan)
|
||||
{
|
||||
u32 m = 1 << chan;
|
||||
int r = (readl(dmac + S6_DMA_PENDCNTIRQSTAT) & m) && 1;
|
||||
if (r)
|
||||
writel(m, dmac + S6_DMA_PENDCNTIRQCLR);
|
||||
return r;
|
||||
}
|
||||
|
||||
static inline int s6dmac_lowwmark_irq(u32 dmac, int chan)
|
||||
{
|
||||
int r = (readl(dmac + S6_DMA_LOWWMRKIRQSTAT) & (1 << chan)) ? 1 : 0;
|
||||
if (r)
|
||||
writel(1 << chan, dmac + S6_DMA_LOWWMRKIRQCLR);
|
||||
return r;
|
||||
}
|
||||
|
||||
static inline u32 s6dmac_pending_count(u32 dmac, int chan)
|
||||
{
|
||||
return (readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL)
|
||||
>> S6_DMA_CHNCTRL_PENDGCNTSTAT)
|
||||
& S6_DMA_CHNCTRL_PENDGCNTSTAT_MASK;
|
||||
}
|
||||
|
||||
static inline void s6dmac_set_terminal_count(u32 dmac, int chan, u32 n)
|
||||
{
|
||||
n &= S6_DMA_TERMCNTNB_MASK;
|
||||
n |= readl(DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB)
|
||||
& ~S6_DMA_TERMCNTNB_MASK;
|
||||
writel(n, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB);
|
||||
}
|
||||
|
||||
static inline u32 s6dmac_get_terminal_count(u32 dmac, int chan)
|
||||
{
|
||||
return (readl(DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB))
|
||||
& S6_DMA_TERMCNTNB_MASK;
|
||||
}
|
||||
|
||||
static inline u32 s6dmac_timestamp(u32 dmac, int chan)
|
||||
{
|
||||
return readl(DMA_CHNL(dmac, chan) + S6_DMA_TIMESTAMP);
|
||||
}
|
||||
|
||||
static inline u32 s6dmac_cur_src(u32 dmac, int chan)
|
||||
{
|
||||
return readl(DMA_CHNL(dmac, chan) + S6_DMA_CUR_SRC);
|
||||
}
|
||||
|
||||
static inline u32 s6dmac_cur_dst(u32 dmac, int chan)
|
||||
{
|
||||
return readl(DMA_CHNL(dmac, chan) + S6_DMA_CUR_DST);
|
||||
}
|
||||
|
||||
static inline void s6dmac_disable_chan(u32 dmac, int chan)
|
||||
{
|
||||
u32 ctrl;
|
||||
writel(readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL)
|
||||
& ~(1 << S6_DMA_CHNCTRL_ENABLE),
|
||||
DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL);
|
||||
do
|
||||
ctrl = readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL);
|
||||
while (ctrl & (1 << S6_DMA_CHNCTRL_ENABLE));
|
||||
}
|
||||
|
||||
static inline void s6dmac_set_stride_skip(u32 dmac, int chan,
|
||||
int comchunk, /* 0: disable scatter/gather */
|
||||
int srcskip, int dstskip)
|
||||
{
|
||||
writel(comchunk, DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK);
|
||||
writel(srcskip, DMA_CHNL(dmac, chan) + S6_DMA_SRCSKIP);
|
||||
writel(dstskip, DMA_CHNL(dmac, chan) + S6_DMA_DSTSKIP);
|
||||
}
|
||||
|
||||
static inline void s6dmac_enable_chan(u32 dmac, int chan,
|
||||
int prio, /* 0 (highest) .. 3 (lowest) */
|
||||
int periphxfer, /* <0: disable p.req.line, 0..1: mode */
|
||||
int srcinc, int dstinc, /* 0: dont increment src/dst address */
|
||||
int comchunk, /* 0: disable scatter/gather */
|
||||
int srcskip, int dstskip,
|
||||
int burstsize, /* 4 for I2S, 7 for everything else */
|
||||
int bandwidthconserve, /* <0: disable, 0..1: select */
|
||||
int lowwmark, /* 0..15 */
|
||||
int timestamp, /* 0: disable timestamp */
|
||||
int enable) /* 0: disable for now */
|
||||
{
|
||||
writel(1, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB);
|
||||
writel(0, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTTMO);
|
||||
writel(lowwmark << S6_DMA_CHNCTRL_LOWWMARK,
|
||||
DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL);
|
||||
s6dmac_set_stride_skip(dmac, chan, comchunk, srcskip, dstskip);
|
||||
writel(((enable ? 1 : 0) << S6_DMA_CHNCTRL_ENABLE) |
|
||||
(prio << S6_DMA_CHNCTRL_PRIO) |
|
||||
(((periphxfer > 0) ? 1 : 0) << S6_DMA_CHNCTRL_PERIPHXFER) |
|
||||
(((periphxfer < 0) ? 0 : 1) << S6_DMA_CHNCTRL_PERIPHENA) |
|
||||
((srcinc ? 1 : 0) << S6_DMA_CHNCTRL_SRCINC) |
|
||||
((dstinc ? 1 : 0) << S6_DMA_CHNCTRL_DSTINC) |
|
||||
(burstsize << S6_DMA_CHNCTRL_BURSTLOG) |
|
||||
(((bandwidthconserve > 0) ? 1 : 0) << S6_DMA_CHNCTRL_BWCONSEL) |
|
||||
(((bandwidthconserve < 0) ? 0 : 1) << S6_DMA_CHNCTRL_BWCONENA) |
|
||||
(lowwmark << S6_DMA_CHNCTRL_LOWWMARK) |
|
||||
((timestamp ? 1 : 0) << S6_DMA_CHNCTRL_TSTAMP),
|
||||
DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL);
|
||||
}
|
||||
|
||||
|
||||
/* DMA control, per engine */
|
||||
|
||||
static inline unsigned _dmac_addr_index(u32 dmac)
|
||||
{
|
||||
unsigned i = S6_DMAC_INDEX(dmac);
|
||||
if (s6dmac_ctrl[i].dmac != dmac)
|
||||
BUG();
|
||||
return i;
|
||||
}
|
||||
|
||||
static inline void _s6dmac_disable_error_irqs(u32 dmac, u32 mask)
|
||||
{
|
||||
writel(mask, dmac + S6_DMA_TERMCNTIRQCLR);
|
||||
writel(mask, dmac + S6_DMA_PENDCNTIRQCLR);
|
||||
writel(mask, dmac + S6_DMA_LOWWMRKIRQCLR);
|
||||
writel(readl(dmac + S6_DMA_INTENABLE0)
|
||||
& ~((mask << S6_DMA_INT0_UNDER) | (mask << S6_DMA_INT0_OVER)),
|
||||
dmac + S6_DMA_INTENABLE0);
|
||||
writel(readl(dmac + S6_DMA_INTENABLE1) & ~(mask << S6_DMA_INT1_CHANNEL),
|
||||
dmac + S6_DMA_INTENABLE1);
|
||||
writel((mask << S6_DMA_INT0_UNDER) | (mask << S6_DMA_INT0_OVER),
|
||||
dmac + S6_DMA_INTCLEAR0);
|
||||
writel(mask << S6_DMA_INT1_CHANNEL, dmac + S6_DMA_INTCLEAR1);
|
||||
}
|
||||
|
||||
/*
|
||||
* request channel from specified engine
|
||||
* with chan<0, accept any channel
|
||||
* further parameters see s6dmac_enable_chan
|
||||
* returns < 0 upon error, channel nb otherwise
|
||||
*/
|
||||
static inline int s6dmac_request_chan(u32 dmac, int chan,
|
||||
int prio,
|
||||
int periphxfer,
|
||||
int srcinc, int dstinc,
|
||||
int comchunk,
|
||||
int srcskip, int dstskip,
|
||||
int burstsize,
|
||||
int bandwidthconserve,
|
||||
int lowwmark,
|
||||
int timestamp,
|
||||
int enable)
|
||||
{
|
||||
int r = chan;
|
||||
unsigned long flags;
|
||||
spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock;
|
||||
spin_lock_irqsave(spinl, flags);
|
||||
if (r < 0) {
|
||||
r = (readl(dmac + S6_DMA_NEXTFREE) >> S6_DMA_NEXTFREE_CHAN)
|
||||
& S6_DMA_NEXTFREE_CHAN_MASK;
|
||||
}
|
||||
if (r >= s6dmac_ctrl[_dmac_addr_index(dmac)].chan_nb) {
|
||||
if (chan < 0)
|
||||
r = -EBUSY;
|
||||
else
|
||||
r = -ENXIO;
|
||||
} else if (((readl(dmac + S6_DMA_NEXTFREE) >> S6_DMA_NEXTFREE_ENA)
|
||||
>> r) & 1) {
|
||||
r = -EBUSY;
|
||||
} else {
|
||||
s6dmac_enable_chan(dmac, r, prio, periphxfer,
|
||||
srcinc, dstinc, comchunk, srcskip, dstskip, burstsize,
|
||||
bandwidthconserve, lowwmark, timestamp, enable);
|
||||
}
|
||||
spin_unlock_irqrestore(spinl, flags);
|
||||
return r;
|
||||
}
|
||||
|
||||
static inline void s6dmac_put_fifo(u32 dmac, int chan,
|
||||
u32 src, u32 dst, u32 size)
|
||||
{
|
||||
unsigned long flags;
|
||||
spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock;
|
||||
spin_lock_irqsave(spinl, flags);
|
||||
writel(src, dmac + S6_DMA_DESCRFIFO0);
|
||||
writel(dst, dmac + S6_DMA_DESCRFIFO1);
|
||||
writel(size, dmac + S6_DMA_DESCRFIFO2);
|
||||
writel(chan, dmac + S6_DMA_DESCRFIFO3);
|
||||
spin_unlock_irqrestore(spinl, flags);
|
||||
}
|
||||
|
||||
static inline u32 s6dmac_channel_enabled(u32 dmac, int chan)
|
||||
{
|
||||
return readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL) &
|
||||
(1 << S6_DMA_CHNCTRL_ENABLE);
|
||||
}
|
||||
|
||||
/*
|
||||
* group 1-4 data port channels
|
||||
* with port=0..3, nrch=1-4 channels,
|
||||
* frrep=0/1 (dis- or enable frame repeat)
|
||||
*/
|
||||
static inline void s6dmac_dp_setup_group(u32 dmac, int port,
|
||||
int nrch, int frrep)
|
||||
{
|
||||
const static u8 mask[4] = {0, 3, 1, 2};
|
||||
BUG_ON(dmac != S6_REG_DPDMA);
|
||||
if ((port < 0) || (port > 3) || (nrch < 1) || (nrch > 4))
|
||||
return;
|
||||
writel((mask[nrch - 1] << S6_DMA_DPORTCTRLGRP_NRCHANS)
|
||||
| ((frrep ? 1 : 0) << S6_DMA_DPORTCTRLGRP_FRAMEREP),
|
||||
dmac + S6_DMA_DPORTCTRLGRP(port));
|
||||
}
|
||||
|
||||
static inline void s6dmac_dp_switch_group(u32 dmac, int port, int enable)
|
||||
{
|
||||
u32 tmp;
|
||||
BUG_ON(dmac != S6_REG_DPDMA);
|
||||
tmp = readl(dmac + S6_DMA_DPORTCTRLGRP(port));
|
||||
if (enable)
|
||||
tmp |= (1 << S6_DMA_DPORTCTRLGRP_ENA);
|
||||
else
|
||||
tmp &= ~(1 << S6_DMA_DPORTCTRLGRP_ENA);
|
||||
writel(tmp, dmac + S6_DMA_DPORTCTRLGRP(port));
|
||||
}
|
||||
|
||||
extern void s6dmac_put_fifo_cache(u32 dmac, int chan,
|
||||
u32 src, u32 dst, u32 size);
|
||||
extern void s6dmac_disable_error_irqs(u32 dmac, u32 mask);
|
||||
extern u32 s6dmac_int_sources(u32 dmac, u32 channel);
|
||||
extern void s6dmac_release_chan(u32 dmac, int chan);
|
||||
|
||||
#endif /* __ASM_XTENSA_S6000_DMAC_H */
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
#ifndef _XTENSA_VARIANT_S6000_GPIO_H
|
||||
#define _XTENSA_VARIANT_S6000_GPIO_H
|
||||
|
||||
extern int s6_gpio_init(void);
|
||||
extern int s6_gpio_init(u32 afsel);
|
||||
|
||||
#endif /* _XTENSA_VARIANT_S6000_GPIO_H */
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
#ifndef __XTENSA_S6000_IRQ_H
|
||||
#define __XTENSA_S6000_IRQ_H
|
||||
#ifndef _XTENSA_S6000_IRQ_H
|
||||
#define _XTENSA_S6000_IRQ_H
|
||||
|
||||
#define NO_IRQ (-1)
|
||||
#define VARIANT_NR_IRQS 8 /* GPIO interrupts */
|
||||
|
||||
extern void variant_irq_enable(unsigned int irq);
|
||||
extern void variant_irq_disable(unsigned int irq);
|
||||
|
||||
#endif /* __XTENSA_S6000_IRQ_H */
|
||||
|
|
|
|||
|
|
@ -2443,6 +2443,17 @@ config JME
|
|||
To compile this driver as a module, choose M here. The module
|
||||
will be called jme.
|
||||
|
||||
config S6GMAC
|
||||
tristate "S6105 GMAC ethernet support"
|
||||
depends on XTENSA_VARIANT_S6000
|
||||
select PHYLIB
|
||||
help
|
||||
This driver supports the on chip ethernet device on the
|
||||
S6105 xtensa processor.
|
||||
|
||||
To compile this driver as a module, choose M here. The module
|
||||
will be called s6gmac.
|
||||
|
||||
endif # NETDEV_1000
|
||||
|
||||
#
|
||||
|
|
|
|||
|
|
@ -245,6 +245,7 @@ obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o
|
|||
|
||||
obj-$(CONFIG_DNET) += dnet.o
|
||||
obj-$(CONFIG_MACB) += macb.o
|
||||
obj-$(CONFIG_S6GMAC) += s6gmac.o
|
||||
|
||||
obj-$(CONFIG_ARM) += arm/
|
||||
obj-$(CONFIG_DEV_APPLETALK) += appletalk/
|
||||
|
|
|
|||
1073
drivers/net/s6gmac.c
Normal file
1073
drivers/net/s6gmac.c
Normal file
File diff suppressed because it is too large
Load Diff
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Reference in New Issue
Block a user