forked from luck/tmp_suning_uos_patched
ARM: S5PV310: Add support CPUFREQ
This patch adds support CPUFREQ driver for S5PV310 and S5PC210. This can support DVFS(Dynamic Voltage and Frequency Scaling). The voltage scaling depends on existence of regulator. Sigend-off-by: Sunyoung Kang <sy0816.kang@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Sunyoung Kang
Kukjin Kim
parent
dd0b7e20da
commit
f40f91fefc
561
arch/arm/mach-s5pv310/cpufreq.c
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561
arch/arm/mach-s5pv310/cpufreq.c
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@ -0,0 +1,561 @@
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/* linux/arch/arm/mach-s5pv310/cpufreq.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* S5PV310 - CPU frequency scaling support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/regulator/consumer.h>
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#include <linux/cpufreq.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-mem.h>
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#include <plat/clock.h>
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static struct clk *cpu_clk;
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static struct clk *moutcore;
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static struct clk *mout_mpll;
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static struct clk *mout_apll;
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#ifdef CONFIG_REGULATOR
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static struct regulator *arm_regulator;
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static struct regulator *int_regulator;
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#endif
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static struct cpufreq_freqs freqs;
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static unsigned int armclk_use_apll;
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static unsigned int memtype;
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enum s5pv310_memory_type {
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DDR2 = 4,
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LPDDR2,
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DDR3,
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};
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enum cpufreq_level_index {
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L0, L1, L2, L3, L4, CPUFREQ_LEVEL_END,
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};
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static struct cpufreq_frequency_table s5pv310_freq_table[] = {
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{L0, 1000*1000},
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{L1, 800*1000},
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{L2, 400*1000},
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{L3, 200*1000},
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{L4, 100*1000},
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{0, CPUFREQ_TABLE_END},
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};
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static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END + 1][7] = {
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/*
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* Clock divider value for following
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* { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
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* DIVATB, DIVPCLK_DBG, DIVAPLL }
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*/
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/* ARM L0: 1000MHz */
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{ 0, 3, 7, 3, 3, 0, 0 },
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/* ARM L1: 800MHz */
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{ 0, 3, 7, 3, 3, 0, 0 },
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/* ARM L2: 400MHz */
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{ 1, 1, 3, 1, 1, 0, 0 },
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/* ARM L3: 200MHz */
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{ 3, 0, 1, 0, 0, 0, 0 },
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/* ARM L4A: 100MHz, for DDR2/3 */
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{ 7, 0, 1, 0, 0, 0, 0 },
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/* ARM L4B: 100MHz, for LPDDR2 (SMDKV310 has LPDDR2) */
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{ 7, 0, 1, 0, 0, 0, 0 },
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};
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static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END + 1][8] = {
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/*
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* Clock divider value for following
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* { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
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* DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
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*/
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/* DMC L0: 400MHz */
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{ 3, 1, 1, 1, 1, 1, 3, 1 },
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/* DMC L1: 400MHz */
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{ 3, 1, 1, 1, 1, 1, 3, 1 },
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/* DMC L2: 400MHz */
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{ 3, 1, 1, 1, 1, 1, 3, 1 },
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/* DMC L3: 400MHz */
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{ 3, 1, 1, 1, 1, 1, 3, 1 },
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/* DMC L4A: 400MHz, for DDR2/3 */
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{ 7, 1, 1, 1, 1, 1, 3, 1 },
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/* DMC L4B: 200MHz, for LPDDR2 */
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{ 7, 1, 1, 3, 1, 1, 3, 1 },
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};
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static unsigned int clkdiv_top[CPUFREQ_LEVEL_END + 1][5] = {
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/*
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* Clock divider value for following
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* { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
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*/
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/* ACLK200 L0: 200MHz */
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{ 3, 7, 4, 5, 1 },
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/* ACLK200 L1: 200MHz */
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{ 3, 7, 4, 5, 1 },
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/* ACLK200 L2: 200MHz */
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{ 3, 7, 4, 5, 1 },
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/* ACLK200 L3: 200MHz */
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{ 3, 7, 4, 5, 1 },
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/* ACLK200 L4A: 100MHz */
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{ 7, 7, 7, 7, 1 },
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/* ACLK200 L4B: 100MHz */
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{ 7, 7, 7, 7, 1 },
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};
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static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END + 1][2] = {
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/*
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* Clock divider value for following
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* { DIVGDL/R, DIVGPL/R }
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*/
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/* ACLK_GDL/R L0: 200MHz */
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{ 3, 1 },
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/* ACLK_GDL/R L1: 200MHz */
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{ 3, 1 },
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/* ACLK_GDL/R L2: 200MHz */
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{ 3, 1 },
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/* ACLK_GDL/R L3: 200MHz */
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{ 3, 1 },
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/* ACLK_GDL/R L4A: 100MHz */
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{ 7, 1 },
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/* ACLK_GDL/R L4B: 100MHz */
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{ 7, 1 },
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};
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struct cpufreq_voltage_table {
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unsigned int index; /* any */
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unsigned int arm_volt; /* uV */
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unsigned int int_volt;
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};
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static struct cpufreq_voltage_table s5pv310_volt_table[] = {
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{
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.index = L0,
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.arm_volt = 1200000,
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.int_volt = 1100000,
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}, {
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.index = L1,
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.arm_volt = 1100000,
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.int_volt = 1100000,
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}, {
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.index = L2,
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.arm_volt = 1050000,
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.int_volt = 1100000,
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}, {
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.index = L3,
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.arm_volt = 1050000,
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.int_volt = 1100000,
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}, {
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.index = L4,
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.arm_volt = 1000000,
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.int_volt = 1000000,
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},
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};
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int s5pv310_verify_speed(struct cpufreq_policy *policy)
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{
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return cpufreq_frequency_table_verify(policy, s5pv310_freq_table);
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}
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unsigned int s5pv310_getspeed(unsigned int cpu)
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{
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return clk_get_rate(cpu_clk) / 1000;
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}
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void s5pv310_set_clkdiv(unsigned int div_index)
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{
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unsigned int tmp;
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/* Change Divider - CPU0 */
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tmp = __raw_readl(S5P_CLKDIV_CPU);
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tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK | S5P_CLKDIV_CPU0_COREM0_MASK |
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S5P_CLKDIV_CPU0_COREM1_MASK | S5P_CLKDIV_CPU0_PERIPH_MASK |
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S5P_CLKDIV_CPU0_ATB_MASK | S5P_CLKDIV_CPU0_PCLKDBG_MASK |
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S5P_CLKDIV_CPU0_APLL_MASK);
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tmp |= ((clkdiv_cpu0[div_index][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) |
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(clkdiv_cpu0[div_index][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) |
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(clkdiv_cpu0[div_index][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) |
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(clkdiv_cpu0[div_index][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) |
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(clkdiv_cpu0[div_index][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) |
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(clkdiv_cpu0[div_index][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) |
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(clkdiv_cpu0[div_index][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));
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__raw_writel(tmp, S5P_CLKDIV_CPU);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STATCPU);
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} while (tmp & 0x1111111);
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/* Change Divider - DMC0 */
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tmp = __raw_readl(S5P_CLKDIV_DMC0);
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tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | S5P_CLKDIV_DMC0_ACPPCLK_MASK |
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S5P_CLKDIV_DMC0_DPHY_MASK | S5P_CLKDIV_DMC0_DMC_MASK |
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S5P_CLKDIV_DMC0_DMCD_MASK | S5P_CLKDIV_DMC0_DMCP_MASK |
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S5P_CLKDIV_DMC0_COPY2_MASK | S5P_CLKDIV_DMC0_CORETI_MASK);
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tmp |= ((clkdiv_dmc0[div_index][0] << S5P_CLKDIV_DMC0_ACP_SHIFT) |
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(clkdiv_dmc0[div_index][1] << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
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(clkdiv_dmc0[div_index][2] << S5P_CLKDIV_DMC0_DPHY_SHIFT) |
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(clkdiv_dmc0[div_index][3] << S5P_CLKDIV_DMC0_DMC_SHIFT) |
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(clkdiv_dmc0[div_index][4] << S5P_CLKDIV_DMC0_DMCD_SHIFT) |
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(clkdiv_dmc0[div_index][5] << S5P_CLKDIV_DMC0_DMCP_SHIFT) |
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(clkdiv_dmc0[div_index][6] << S5P_CLKDIV_DMC0_COPY2_SHIFT) |
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(clkdiv_dmc0[div_index][7] << S5P_CLKDIV_DMC0_CORETI_SHIFT));
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__raw_writel(tmp, S5P_CLKDIV_DMC0);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
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} while (tmp & 0x11111111);
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/* Change Divider - TOP */
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tmp = __raw_readl(S5P_CLKDIV_TOP);
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tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK | S5P_CLKDIV_TOP_ACLK100_MASK |
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S5P_CLKDIV_TOP_ACLK160_MASK | S5P_CLKDIV_TOP_ACLK133_MASK |
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S5P_CLKDIV_TOP_ONENAND_MASK);
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tmp |= ((clkdiv_top[div_index][0] << S5P_CLKDIV_TOP_ACLK200_SHIFT) |
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(clkdiv_top[div_index][1] << S5P_CLKDIV_TOP_ACLK100_SHIFT) |
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(clkdiv_top[div_index][2] << S5P_CLKDIV_TOP_ACLK160_SHIFT) |
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(clkdiv_top[div_index][3] << S5P_CLKDIV_TOP_ACLK133_SHIFT) |
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(clkdiv_top[div_index][4] << S5P_CLKDIV_TOP_ONENAND_SHIFT));
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__raw_writel(tmp, S5P_CLKDIV_TOP);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
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} while (tmp & 0x11111);
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/* Change Divider - LEFTBUS */
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tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
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tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
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tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
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(clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
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__raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
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} while (tmp & 0x11);
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/* Change Divider - RIGHTBUS */
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tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
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tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
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tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
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(clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
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__raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
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} while (tmp & 0x11);
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}
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static int s5pv310_target(struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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{
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unsigned int index, div_index, tmp;
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unsigned int arm_volt, int_volt;
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unsigned int need_apll = 0;
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freqs.old = s5pv310_getspeed(policy->cpu);
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if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
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target_freq, relation, &index))
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return -EINVAL;
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freqs.new = s5pv310_freq_table[index].frequency;
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freqs.cpu = policy->cpu;
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if (freqs.new == freqs.old)
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return 0;
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/*
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* If freqs.new is higher than 800MHz
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* cpufreq driver should turn on apll
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*/
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if (index < L1)
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need_apll = 1;
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/* If the memory type is LPDDR2, use L4-B instead of L4-A */
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if ((index == L4) && (memtype == LPDDR2))
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div_index = index + 1;
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else
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div_index = index;
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/* get the voltage value */
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arm_volt = s5pv310_volt_table[index].arm_volt;
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int_volt = s5pv310_volt_table[index].int_volt;
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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/* control regulator */
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if (freqs.new > freqs.old) {
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/* Voltage up */
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#ifdef CONFIG_REGULATOR
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regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
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regulator_set_voltage(int_regulator, int_volt, int_volt);
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#endif
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}
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/* Clock Configuration Procedure */
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/* 1. Change the system clock divider values */
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s5pv310_set_clkdiv(div_index);
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/* 2. Change the divider values for special clocks in CMU_TOP */
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/* currently nothing */
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/* 3. Change the XPLL values or Select the parent XPLL */
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if (need_apll) {
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if (!armclk_use_apll) {
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/*
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* If the parent clock of armclk isn't apll
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* here need to set apll (include m,p,s value)
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*/
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/* a. MUX_CORE_SEL = MPLL,
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* ARMCLK uses MPLL for lock time */
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clk_set_parent(moutcore, mout_mpll);
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do {
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tmp = (__raw_readl(S5P_CLKMUX_STATCPU)
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>> S5P_CLKSRC_CPU_MUXCORE_SHIFT);
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tmp &= 0x7;
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} while (tmp != 0x2);
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/* b. Set APLL Lock time */
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__raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK);
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/* c. Change PLL PMS values */
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__raw_writel(S5P_APLL_VAL_1000, S5P_APLL_CON0);
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/* d. Turn on a PLL */
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tmp = __raw_readl(S5P_APLL_CON0);
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tmp |= (0x1 << S5P_APLLCON0_ENABLE_SHIFT);
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__raw_writel(tmp, S5P_APLL_CON0);
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/* e. wait_lock_time */
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do {
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tmp = __raw_readl(S5P_APLL_CON0);
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} while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT)));
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armclk_use_apll = 1;
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}
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/* MUX_CORE_SEL = APLL */
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clk_set_parent(moutcore, mout_apll);
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do {
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tmp = __raw_readl(S5P_CLKMUX_STATCPU);
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tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
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} while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
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} else {
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if (clk_get_parent(moutcore) != mout_mpll) {
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clk_set_parent(moutcore, mout_mpll);
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do {
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tmp = __raw_readl(S5P_CLKMUX_STATCPU);
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tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
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} while (tmp != (0x2 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
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}
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}
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/* control regulator */
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if (freqs.new < freqs.old) {
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/* Voltage down */
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#ifdef CONFIG_REGULATOR
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regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
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regulator_set_voltage(int_regulator, int_volt, int_volt);
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#endif
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}
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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return 0;
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}
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#ifdef CONFIG_PM
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static int s5pv310_cpufreq_suspend(struct cpufreq_policy *policy,
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pm_message_t pmsg)
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{
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return 0;
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}
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static int s5pv310_cpufreq_resume(struct cpufreq_policy *policy)
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{
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return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int s5pv310_cpufreq_cpu_init(struct cpufreq_policy *policy)
|
||||
{
|
||||
policy->cur = policy->min = policy->max = s5pv310_getspeed(policy->cpu);
|
||||
|
||||
cpufreq_frequency_table_get_attr(s5pv310_freq_table, policy->cpu);
|
||||
|
||||
/* set the transition latency value */
|
||||
policy->cpuinfo.transition_latency = 100000;
|
||||
|
||||
/*
|
||||
* S5PV310 multi-core processors has 2 cores
|
||||
* that the frequency cannot be set independently.
|
||||
* Each cpu is bound to the same speed.
|
||||
* So the affected cpu is all of the cpus.
|
||||
*/
|
||||
cpumask_setall(policy->cpus);
|
||||
|
||||
return cpufreq_frequency_table_cpuinfo(policy, s5pv310_freq_table);
|
||||
}
|
||||
|
||||
static struct cpufreq_driver s5pv310_driver = {
|
||||
.flags = CPUFREQ_STICKY,
|
||||
.verify = s5pv310_verify_speed,
|
||||
.target = s5pv310_target,
|
||||
.get = s5pv310_getspeed,
|
||||
.init = s5pv310_cpufreq_cpu_init,
|
||||
.name = "s5pv310_cpufreq",
|
||||
#ifdef CONFIG_PM
|
||||
.suspend = s5pv310_cpufreq_suspend,
|
||||
.resume = s5pv310_cpufreq_resume,
|
||||
#endif
|
||||
};
|
||||
|
||||
static int __init s5pv310_cpufreq_init(void)
|
||||
{
|
||||
unsigned int tmp;
|
||||
|
||||
cpu_clk = clk_get(NULL, "armclk");
|
||||
if (IS_ERR(cpu_clk))
|
||||
return PTR_ERR(cpu_clk);
|
||||
|
||||
moutcore = clk_get(NULL, "moutcore");
|
||||
if (IS_ERR(moutcore))
|
||||
goto out;
|
||||
|
||||
mout_mpll = clk_get(NULL, "mout_mpll");
|
||||
if (IS_ERR(mout_mpll))
|
||||
goto out;
|
||||
|
||||
mout_apll = clk_get(NULL, "mout_apll");
|
||||
if (IS_ERR(mout_apll))
|
||||
goto out;
|
||||
|
||||
#ifdef CONFIG_REGULATOR
|
||||
arm_regulator = regulator_get(NULL, "vdd_arm");
|
||||
if (IS_ERR(arm_regulator)) {
|
||||
printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
|
||||
goto out;
|
||||
}
|
||||
|
||||
int_regulator = regulator_get(NULL, "vdd_int");
|
||||
if (IS_ERR(int_regulator)) {
|
||||
printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
|
||||
goto out;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* check parent clock of armclk */
|
||||
tmp = __raw_readl(S5P_CLKSRC_CPU);
|
||||
if (tmp & S5P_CLKSRC_CPU_MUXCORE_SHIFT)
|
||||
armclk_use_apll = 0;
|
||||
else
|
||||
armclk_use_apll = 1;
|
||||
|
||||
/*
|
||||
* Check DRAM type.
|
||||
* Because DVFS level is different according to DRAM type.
|
||||
*/
|
||||
memtype = __raw_readl(S5P_VA_DMC0 + S5P_DMC0_MEMCON_OFFSET);
|
||||
memtype = (memtype >> S5P_DMC0_MEMTYPE_SHIFT);
|
||||
memtype &= S5P_DMC0_MEMTYPE_MASK;
|
||||
|
||||
if ((memtype < DDR2) && (memtype > DDR3)) {
|
||||
printk(KERN_ERR "%s: wrong memtype= 0x%x\n", __func__, memtype);
|
||||
goto out;
|
||||
} else {
|
||||
printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
|
||||
}
|
||||
|
||||
return cpufreq_register_driver(&s5pv310_driver);
|
||||
|
||||
out:
|
||||
if (!IS_ERR(cpu_clk))
|
||||
clk_put(cpu_clk);
|
||||
|
||||
if (!IS_ERR(moutcore))
|
||||
clk_put(moutcore);
|
||||
|
||||
if (!IS_ERR(mout_mpll))
|
||||
clk_put(mout_mpll);
|
||||
|
||||
if (!IS_ERR(mout_apll))
|
||||
clk_put(mout_apll);
|
||||
|
||||
#ifdef CONFIG_REGULATOR
|
||||
if (!IS_ERR(arm_regulator))
|
||||
regulator_put(arm_regulator);
|
||||
|
||||
if (!IS_ERR(int_regulator))
|
||||
regulator_put(int_regulator);
|
||||
#endif
|
||||
|
||||
printk(KERN_ERR "%s: failed initialization\n", __func__);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
late_initcall(s5pv310_cpufreq_init);
|
||||
Loading…
Reference in New Issue
Block a user